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9a6de4cb3e
On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions. |
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| .. | ||
| debug_helpers.c | ||
| debug_stubs.c | ||
| esp_ipc_isr_handler.S | ||
| esp_ipc_isr_port.c | ||
| esp_ipc_isr_routines.c | ||
| expression_with_stack.c | ||
| panic_arch.c | ||