Marius Vikhammer 9a6de4cb3e fix(panic): fixed cache error being reported as illegal instruction ... On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions.		2023-12-04 10:49:00 +08:00
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critical_section.h	feat(esp_system): base support on p4	2023-07-25 05:59:10 +00:00
crosscore_int.h	esp32h4: removed esp32h4 related codes	2023-04-23 12:03:07 +00:00
dbg_stubs.h	gcov: add stub table size entry	2021-08-20 15:00:55 +08:00
eh_frame_parser.h	System: implement libunwind library for RISC-V backtracing	2023-05-15 11:19:03 +08:00
esp_int_wdt.h	wdt: add support for H2	2023-02-23 11:22:51 +08:00
esp_ipc_isr.h	feat(esp_system): Support IPC_ISR for ESP32P4	2023-09-15 23:38:12 +08:00
esp_task_wdt_impl.h	TWDT: refactor the TWDT to be driver agnostic	2022-09-15 14:37:59 +08:00
esp_task_wdt.h	TWDT: the Kconfig option ESP_TASK_WDT_EN is now used to enable Task Watchdog	2022-09-15 14:37:59 +08:00
panic_internal.h	fix(panic): fixed cache error being reported as illegal instruction	2023-12-04 10:49:00 +08:00
startup_internal.h	hal: Deprecate interrupt_controller_hal.h, cpu_hal.h and cpu_ll.h interfaces	2022-07-22 00:06:06 +08:00
system_internal.h	System: remove digital-system reset within OS restart when Memprot on	2023-06-26 20:22:59 +02:00
usb_console.h	esp_system: usb_console support for ESP32-S3	2023-04-12 11:17:41 +02:00