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https://github.com/espressif/esp-idf.git
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647dea9395
During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
111 lines
3.9 KiB
C
111 lines
3.9 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include "hal/spi_flash_hal.h"
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#include "string.h"
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#include "soc/soc_caps.h"
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#include "hal/hal_defs.h"
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#define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
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static const char TAG[] = "FLASH_HAL";
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typedef struct {
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int freq;
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spi_flash_ll_clock_reg_t clock_reg_val;
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} spi_flash_hal_clock_config_t;
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static const spi_flash_hal_clock_config_t spi_flash_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
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{5e6, SPI_FLASH_LL_CLKREG_VAL_5MHZ},
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{10e6, SPI_FLASH_LL_CLKREG_VAL_10MHZ},
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{20e6, SPI_FLASH_LL_CLKREG_VAL_20MHZ},
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{26e6, SPI_FLASH_LL_CLKREG_VAL_26MHZ},
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{40e6, SPI_FLASH_LL_CLKREG_VAL_40MHZ},
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{80e6, SPI_FLASH_LL_CLKREG_VAL_80MHZ},
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};
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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static const spi_flash_hal_clock_config_t spi_flash_gpspi_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
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{5e6, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_5MHZ}},
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{10e6, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_10MHZ}},
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{20e6, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_20MHZ}},
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{26e6, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_26MHZ}},
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{40e6, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_40MHZ}},
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{80e6, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_80MHZ}},
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};
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#endif
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static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk)
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{
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const int apbclk_kHz = APB_CLK_FREQ / 1000;
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//calculate how many apb clocks a period has
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const int apbclk_n = APB_CLK_FREQ / eff_clk;
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const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0;
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//calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off.
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int apb_period_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000;
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if (apb_period_n < 0) {
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apb_period_n = 0;
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}
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return apb_period_n / apbclk_n;
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}
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esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg)
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{
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if (!esp_ptr_internal(data_out) && cfg->host_id == SPI1_HOST) {
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return ESP_ERR_INVALID_ARG;
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}
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if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
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return ESP_ERR_INVALID_ARG;
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}
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spi_flash_hal_clock_config_t clock_cfg = spi_flash_clk_cfg_reg[cfg->speed];
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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if (cfg->host_id > SPI_HOST) {
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clock_cfg = spi_flash_gpspi_clk_cfg_reg[cfg->speed];
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}
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#endif
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*data_out = (spi_flash_hal_context_t) {
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.inst = data_out->inst, // Keeps the function pointer table
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.spi = spi_flash_ll_get_hw(cfg->host_id),
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.cs_num = cfg->cs_num,
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.extra_dummy = get_dummy_n(!cfg->iomux, cfg->input_delay_ns, clock_cfg.freq),
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.clock_conf = clock_cfg.clock_reg_val,
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};
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ESP_EARLY_LOGD(TAG, "extra_dummy: %d", data_out->extra_dummy);
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return ESP_OK;
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}
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bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p)
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{
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bool direct_write = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI_HOST)
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|| esp_ptr_in_dram(p) );
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return direct_write;
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}
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bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p)
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{
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//currently the host doesn't support to read through dma, no word-aligned requirements
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bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI_HOST)
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|| esp_ptr_in_dram(p) );
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return direct_read;
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}
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