mirror of
https://github.com/espressif/esp-idf.git
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327 lines
9.1 KiB
C
327 lines
9.1 KiB
C
/**
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Registers */
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/** Type of rom_table_lock register
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* register description
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*/
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typedef union {
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struct {
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/** rom_table_lock : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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uint32_t rom_table_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_rom_table_lock_reg_t;
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/** Type of rom_table register
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* register description
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*/
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typedef union {
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struct {
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/** rom_table : R/W; bitpos: [31:0]; default: 0;
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* Need add description
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*/
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uint32_t rom_table:32;
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};
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uint32_t val;
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} sensitive_rom_table_reg_t;
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/** Type of apb_peripheral_access_0 register
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* register description
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*/
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typedef union {
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struct {
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/** apb_peripheral_access_lock : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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uint32_t apb_peripheral_access_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_apb_peripheral_access_0_reg_t;
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/** Type of apb_peripheral_access_1 register
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* register description
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*/
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typedef union {
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struct {
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/** apb_peripheral_access_split_burst : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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uint32_t apb_peripheral_access_split_burst:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_apb_peripheral_access_1_reg_t;
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/** Type of internal_sram_usage_0 register
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* register description
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*/
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typedef union {
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struct {
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/** internal_sram_usage_lock : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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uint32_t internal_sram_usage_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_internal_sram_usage_0_reg_t;
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/** Type of internal_sram_usage_1 register
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* register description
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*/
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typedef union {
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struct {
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/** internal_sram_usage_cpu_cache : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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uint32_t internal_sram_usage_cpu_cache:1;
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/** internal_sram_usage_cpu_sram : R/W; bitpos: [3:1]; default: 7;
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* Need add description
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*/
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uint32_t internal_sram_usage_cpu_sram:3;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} sensitive_internal_sram_usage_1_reg_t;
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/** Type of internal_sram_usage_3 register
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* register description
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*/
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typedef union {
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struct {
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/** internal_sram_usage_mac_dump_sram : R/W; bitpos: [2:0]; default: 0;
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* Need add description
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*/
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uint32_t internal_sram_usage_mac_dump_sram:3;
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/** internal_sram_alloc_mac_dump : R/W; bitpos: [3]; default: 0;
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* Need add description
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*/
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uint32_t internal_sram_alloc_mac_dump:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} sensitive_internal_sram_usage_3_reg_t;
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/** Type of cache_tag_access_0 register
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* register description
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*/
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typedef union {
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struct {
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/** cache_tag_access_lock : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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uint32_t cache_tag_access_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_cache_tag_access_0_reg_t;
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/** Type of cache_tag_access_1 register
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* register description
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*/
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typedef union {
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struct {
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/** pro_i_tag_rd_acs : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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uint32_t pro_i_tag_rd_acs:1;
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/** pro_i_tag_wr_acs : R/W; bitpos: [1]; default: 1;
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* Need add description
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*/
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uint32_t pro_i_tag_wr_acs:1;
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/** pro_d_tag_rd_acs : R/W; bitpos: [2]; default: 1;
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* Need add description
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*/
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uint32_t pro_d_tag_rd_acs:1;
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/** pro_d_tag_wr_acs : R/W; bitpos: [3]; default: 1;
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* Need add description
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*/
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uint32_t pro_d_tag_wr_acs:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} sensitive_cache_tag_access_1_reg_t;
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/** Type of cache_mmu_access_0 register
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* register description
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*/
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typedef union {
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struct {
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/** cache_mmu_access_lock : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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uint32_t cache_mmu_access_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_cache_mmu_access_0_reg_t;
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/** Type of cache_mmu_access_1 register
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* register description
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*/
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typedef union {
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struct {
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/** pro_mmu_rd_acs : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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uint32_t pro_mmu_rd_acs:1;
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/** pro_mmu_wr_acs : R/W; bitpos: [1]; default: 1;
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* Need add description
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*/
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uint32_t pro_mmu_wr_acs:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} sensitive_cache_mmu_access_1_reg_t;
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/** Type of pif_access_monitor_0 register
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* register description
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*/
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typedef union {
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struct {
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/** pif_access_monitor_lock : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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uint32_t pif_access_monitor_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_pif_access_monitor_0_reg_t;
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/** Type of pif_access_monitor_1 register
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* register description
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*/
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typedef union {
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struct {
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/** pif_access_monitor_nonword_violate_clr : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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uint32_t pif_access_monitor_nonword_violate_clr:1;
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/** pif_access_monitor_nonword_violate_en : R/W; bitpos: [1]; default: 1;
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* Need add description
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*/
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uint32_t pif_access_monitor_nonword_violate_en:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} sensitive_pif_access_monitor_1_reg_t;
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/** Type of pif_access_monitor_2 register
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* register description
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*/
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typedef union {
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struct {
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/** pif_access_monitor_nonword_violate_intr : RO; bitpos: [0]; default: 0;
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* Need add description
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*/
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uint32_t pif_access_monitor_nonword_violate_intr:1;
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/** pif_access_monitor_nonword_violate_status_hsize : RO; bitpos: [2:1]; default: 0;
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* Need add description
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*/
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uint32_t pif_access_monitor_nonword_violate_status_hsize:2;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} sensitive_pif_access_monitor_2_reg_t;
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/** Type of pif_access_monitor_3 register
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* register description
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*/
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typedef union {
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struct {
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/** pif_access_monitor_nonword_violate_status_haddr : RO; bitpos: [31:0]; default: 0;
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* Need add description
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*/
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uint32_t pif_access_monitor_nonword_violate_status_haddr:32;
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};
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uint32_t val;
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} sensitive_pif_access_monitor_3_reg_t;
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/** Type of xts_aes_key_update register
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* register description
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*/
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typedef union {
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struct {
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/** xts_aes_key_update : R/W; bitpos: [0]; default: 0;
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* Set this bit to update xts_aes key
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*/
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uint32_t xts_aes_key_update:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_xts_aes_key_update_reg_t;
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/** Type of clock_gate register
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* register description
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sensitive_clock_gate_reg_t;
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/** Type of sensitive_reg_date register
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* register description
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*/
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typedef union {
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struct {
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/** sensitive_reg_date : R/W; bitpos: [27:0]; default: 34628353;
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* Need add description
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*/
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uint32_t sensitive_reg_date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} sensitive_sensitive_reg_date_reg_t;
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typedef struct {
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volatile sensitive_rom_table_lock_reg_t rom_table_lock;
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volatile sensitive_rom_table_reg_t rom_table;
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volatile sensitive_apb_peripheral_access_0_reg_t apb_peripheral_access_0;
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volatile sensitive_apb_peripheral_access_1_reg_t apb_peripheral_access_1;
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volatile sensitive_internal_sram_usage_0_reg_t internal_sram_usage_0;
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volatile sensitive_internal_sram_usage_1_reg_t internal_sram_usage_1;
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volatile sensitive_internal_sram_usage_3_reg_t internal_sram_usage_3;
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volatile sensitive_cache_tag_access_0_reg_t cache_tag_access_0;
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volatile sensitive_cache_tag_access_1_reg_t cache_tag_access_1;
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volatile sensitive_cache_mmu_access_0_reg_t cache_mmu_access_0;
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volatile sensitive_cache_mmu_access_1_reg_t cache_mmu_access_1;
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volatile sensitive_pif_access_monitor_0_reg_t pif_access_monitor_0;
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volatile sensitive_pif_access_monitor_1_reg_t pif_access_monitor_1;
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volatile sensitive_pif_access_monitor_2_reg_t pif_access_monitor_2;
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volatile sensitive_pif_access_monitor_3_reg_t pif_access_monitor_3;
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volatile sensitive_xts_aes_key_update_reg_t xts_aes_key_update;
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volatile sensitive_clock_gate_reg_t clock_gate;
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uint32_t reserved_044[1006];
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volatile sensitive_sensitive_reg_date_reg_t sensitive_reg_date;
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} sensitive_dev_t;
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#ifndef __cplusplus
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_Static_assert(sizeof(sensitive_dev_t) == 0x1000, "Invalid size of sensitive_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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