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Cache effects on microbenchmarks in cached flash can be significant, depending on linker layout in flash.
28 lines
1.6 KiB
C
28 lines
1.6 KiB
C
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/* @brief macro to print IDF performance
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* @param mode : performance item name. a string pointer.
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* @param value_fmt: print format and unit of the value, for example: "%02fms", "%dKB"
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* @param value : the performance value.
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*/
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#define IDF_LOG_PERFORMANCE(item, value_fmt, value) \
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printf("[Performance][%s]: "value_fmt"\n", item, value)
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/* declare the performance here */
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#define IDF_PERFORMANCE_MAX_HTTPS_REQUEST_BIN_SIZE 800
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 200
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM 270
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 130
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#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL 1000
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 27
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/* Due to code size & linker layout differences interacting with cache, VFS
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microbenchmark currently runs slower with PSRAM enabled. */
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 20000
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM 40000
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// throughput performance by iperf
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#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT 50
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#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT 40
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#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT 80
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#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT 50
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