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45badf864f
Previously, IDF FreeRTOS would restrict the clean up of task memory (done by vTaskDelete() or the Idle task) to only tasks pinned to the current core or unpinned tasks. This was due to the need to clear the task's coprocessor ownership on the other core (i.e., "_xt_coproc_owner_sa"). But this restriction can be lifted by simply protecting access of "_xt_coproc_owner_sa" with a spinlock. This commit implements a "_xt_coproc_owner_sa_lock" to protect the access of "_xt_coproc_owner_sa", thus vTaskDelete() and prvDeleteTCB() can now delete tasks pinned to the other core so long as that task is not currently running. Note: This fix was copied from the Xtensa port of Amazon SMP FreeRTOS
138 lines
4.2 KiB
C
138 lines
4.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*/
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/* File adapted to use on IDF FreeRTOS component, extracted
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* originally from zephyr RTOS code base:
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* https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
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*/
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#ifndef __XT_ASM_UTILS_H
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#define __XT_ASM_UTILS_H
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/*
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* SPILL_ALL_WINDOWS
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*
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* Spills all windowed registers (i.e. registers not visible as
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* A0-A15) to their ABI-defined spill regions on the stack.
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*
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* Unlike the Xtensa HAL implementation, this code requires that the
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* EXCM and WOE bit be enabled in PS, and relies on repeated hardware
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* exception handling to do the register spills. The trick is to do a
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* noop write to the high registers, which the hardware will trap
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* (into an overflow exception) in the case where those registers are
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* already used by an existing call frame. Then it rotates the window
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* and repeats until all but the A0-A3 registers of the original frame
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* are guaranteed to be spilled, eventually rotating back around into
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* the original frame. Advantages:
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*
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* - Vastly smaller code size
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*
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* - More easily maintained if changes are needed to window over/underflow
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* exception handling.
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*
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* - Requires no scratch registers to do its work, so can be used safely in any
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* context.
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*
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* - If the WOE bit is not enabled (for example, in code written for
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* the CALL0 ABI), this becomes a silent noop and operates compatbily.
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*
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* - Hilariously it's ACTUALLY FASTER than the HAL routine. And not
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* just a little bit, it's MUCH faster. With a mostly full register
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* file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
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* registers with this vs. 279 (!) to do it with
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* xthal_spill_windows().
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*/
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.macro SPILL_ALL_WINDOWS
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#if XCHAL_NUM_AREGS == 64
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 4
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#elif XCHAL_NUM_AREGS == 32
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a4, a4, a4
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rotw 2
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#else
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#error Unrecognized XCHAL_NUM_AREGS
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#endif
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.endm
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/*
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--------------------------------------------------------------------------------
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Macro spinlock_take
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This macro will repeatedley attempt to atomically set a spinlock variable
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using the s32c1i instruciton. A spinlock is considered free if its value is 0.
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Entry:
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- "reg_A/B" as scratch registers
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- "lock_var" spinlock variable's symbol
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- Interrupts must already be disabled by caller
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Exit:
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- Spinlock set to current core's ID (PRID)
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- "reg_A/B" clobbered
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--------------------------------------------------------------------------------
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*/
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#if portNUM_PROCESSORS > 1
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.macro spinlock_take reg_A reg_B lock_var
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movi \reg_A, \lock_var /* reg_A = &lock_var */
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.L_spinlock_loop:
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movi \reg_B, 0 /* Load spinlock free value (0) into SCOMPARE1 */
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wsr \reg_B, SCOMPARE1
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rsync /* Ensure that SCOMPARE1 is set before s32c1i executes */
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rsr \reg_B, PRID /* Load the current core's ID into reg_B */
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s32c1i \reg_B, \reg_A, 0 /* Attempt *lock_var = reg_B */
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bnez \reg_B, .L_spinlock_loop /* If the write was successful (i.e., lock was free), 0 will have been written back to reg_B */
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.endm
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#endif /* portNUM_PROCESSORS > 1 */
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/*
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--------------------------------------------------------------------------------
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Macro spinlock_release
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This macro will release a spinlock variable previously taken by the
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spinlock_take macro.
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Entry:
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- "reg_A/B" as scratch registers
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- "lock_var" spinlock variable's symbol
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- Interrupts must already be disabled by caller
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Exit:
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- "reg_A/B" clobbered
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--------------------------------------------------------------------------------
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*/
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#if portNUM_PROCESSORS > 1
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.macro spinlock_release reg_A reg_B lock_var
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movi \reg_A, \lock_var /* reg_A = &lock_var */
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movi \reg_B, 0
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s32i \reg_B, \reg_A, 0 /* Release the spinlock (*reg_A = 0) */
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.endm
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#endif /* portNUM_PROCESSORS > 1 */
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#endif /* __XT_ASM_UTILS_H */
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