mirror of
https://github.com/espressif/esp-idf.git
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515 lines
20 KiB
C
515 lines
20 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "soc/adc_periph.h"
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#include "esp_adc/adc_oneshot.h"
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#include "esp_adc/adc_monitor.h"
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#include "driver/gpio.h"
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#include "driver/rtc_io.h"
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#include "test_common_adc.h"
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#include "esp_rom_sys.h"
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const __attribute__((unused)) static char *TAG = "TEST_ADC";
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/*---------------------------------------------------------------
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ADC General Macros
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---------------------------------------------------------------*/
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//ADC Channels
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#if CONFIG_IDF_TARGET_ESP32
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#define ADC1_TEST_CHAN0 ADC_CHANNEL_4
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#define ADC1_TEST_CHAN1 ADC_CHANNEL_5
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#define ADC2_TEST_CHAN0 ADC_CHANNEL_0
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static const char *TAG_CH[2][10] = {{"ADC1_CH4", "ADC1_CH5"}, {"ADC2_CH0"}};
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#else
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#define ADC1_TEST_CHAN0 ADC_CHANNEL_2
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#define ADC1_TEST_CHAN1 ADC_CHANNEL_3
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#define ADC2_TEST_CHAN0 ADC_CHANNEL_0
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static const char *TAG_CH[2][10] = {{"ADC1_CH2", "ADC1_CH3"}, {"ADC2_CH0"}};
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#endif
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/*---------------------------------------------------------------
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ADC Oneshot High / Low test
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---------------------------------------------------------------*/
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//ESP32C3 ADC2 oneshot mode is not supported anymore
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#define ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2 ((SOC_ADC_PERIPH_NUM >= 2) && !CONFIG_IDF_TARGET_ESP32C3)
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TEST_CASE("ADC oneshot high/low test", "[adc_oneshot]")
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{
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static int adc_raw[2][10];
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//-------------ADC1 Init---------------//
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adc_oneshot_unit_handle_t adc1_handle;
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adc_oneshot_unit_init_cfg_t init_config1 = {
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.unit_id = ADC_UNIT_1,
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.ulp_mode = ADC_ULP_MODE_DISABLE,
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};
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TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &adc1_handle));
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#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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//-------------ADC2 Init---------------//
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adc_oneshot_unit_handle_t adc2_handle;
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adc_oneshot_unit_init_cfg_t init_config2 = {
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.unit_id = ADC_UNIT_2,
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.ulp_mode = ADC_ULP_MODE_DISABLE,
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};
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TEST_ESP_OK(adc_oneshot_new_unit(&init_config2, &adc2_handle));
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#endif //#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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//-------------ADC1 TEST Channel 0 Config---------------//
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adc_oneshot_chan_cfg_t config = {
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.bitwidth = ADC_BITWIDTH_DEFAULT,
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.atten = ADC_ATTEN_DB_12,
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};
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TEST_ESP_OK(adc_oneshot_config_channel(adc1_handle, ADC1_TEST_CHAN0, &config));
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//-------------ADC1 TEST Channel 1 Config---------------//
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TEST_ESP_OK(adc_oneshot_config_channel(adc1_handle, ADC1_TEST_CHAN1, &config));
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#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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//-------------ADC2 TEST Channel 0 Config---------------//
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TEST_ESP_OK(adc_oneshot_config_channel(adc2_handle, ADC2_TEST_CHAN0, &config));
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#endif //#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 0);
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TEST_ESP_OK(adc_oneshot_read(adc1_handle, ADC1_TEST_CHAN0, &adc_raw[0][0]));
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ESP_LOGI(TAG_CH[0][0], "raw data: %d", adc_raw[0][0]);
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TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, adc_raw[0][0]);
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN1, 1);
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TEST_ESP_OK(adc_oneshot_read(adc1_handle, ADC1_TEST_CHAN1, &adc_raw[0][1]));
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ESP_LOGI(TAG_CH[0][1], "raw data: %d", adc_raw[0][1]);
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TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, adc_raw[0][1]);
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#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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test_adc_set_io_level(ADC_UNIT_2, ADC2_TEST_CHAN0, 0);
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TEST_ESP_OK(adc_oneshot_read(adc2_handle, ADC2_TEST_CHAN0, &adc_raw[1][0]));
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ESP_LOGI(TAG_CH[1][0], "raw data: %d", adc_raw[1][0]);
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TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, adc_raw[1][0]);
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#endif //#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 1);
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TEST_ESP_OK(adc_oneshot_read(adc1_handle, ADC1_TEST_CHAN0, &adc_raw[0][0]));
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ESP_LOGI(TAG_CH[0][0], "raw data: %d", adc_raw[0][0]);
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TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, adc_raw[0][0]);
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN1, 0);
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TEST_ESP_OK(adc_oneshot_read(adc1_handle, ADC1_TEST_CHAN1, &adc_raw[0][1]));
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ESP_LOGI(TAG_CH[0][1], "raw data: %d", adc_raw[0][1]);
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TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, adc_raw[0][1]);
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#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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test_adc_set_io_level(ADC_UNIT_2, ADC2_TEST_CHAN0, 1);
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TEST_ESP_OK(adc_oneshot_read(adc2_handle, ADC2_TEST_CHAN0, &adc_raw[1][0]));
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ESP_LOGI(TAG_CH[1][0], "raw data: %d", adc_raw[1][0]);
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TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, adc_raw[1][0]);
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#endif //#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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TEST_ESP_OK(adc_oneshot_del_unit(adc1_handle));
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#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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TEST_ESP_OK(adc_oneshot_del_unit(adc2_handle));
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#endif //#if ADC_TEST_ONESHOT_HIGH_LOW_TEST_ADC2
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}
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TEST_CASE("ADC oneshot stress test that get zero even if convent done", "[adc_oneshot]")
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{
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//There is a hardware limitation. After ADC get DONE signal, it still need a delay to synchronize ADC raw data or it may get zero even if getting DONE signal.
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int test_num = 100;
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adc_channel_t channel = ADC1_TEST_CHAN1;
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adc_atten_t atten = ADC_ATTEN_DB_12;
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adc_unit_t unit_id = ADC_UNIT_1;
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adc_oneshot_unit_handle_t adc1_handle;
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adc_oneshot_unit_init_cfg_t init_config1 = {
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.unit_id = unit_id,
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.ulp_mode = ADC_ULP_MODE_DISABLE,
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};
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adc_oneshot_chan_cfg_t config = {
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.bitwidth = SOC_ADC_RTC_MAX_BITWIDTH,
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.atten = atten,
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};
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int raw_data = 0;
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srand(199);
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for (int i = 0; i < test_num; i++) {
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test_adc_set_io_level(unit_id, ADC1_TEST_CHAN1, 1);
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TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &adc1_handle));
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TEST_ESP_OK(adc_oneshot_config_channel(adc1_handle, channel, &config));
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TEST_ESP_OK(adc_oneshot_read(adc1_handle, channel, &raw_data));
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TEST_ASSERT_NOT_EQUAL(0, raw_data);
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TEST_ESP_OK(adc_oneshot_del_unit(adc1_handle));
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esp_rom_delay_us(rand() % 512);
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}
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}
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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/*---------------------------------------------------------------
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ADC Oneshot with Light Sleep
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---------------------------------------------------------------*/
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#include <inttypes.h>
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#include "esp_sleep.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "soc/regi2c_saradc.h"
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#define TEST_REGI2C_ANA_CALI_BYTE_NUM 8
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static void s_adc_oneshot_with_sleep(adc_unit_t unit_id, adc_channel_t channel)
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{
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//-------------ADC Init---------------//
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adc_oneshot_unit_handle_t adc_handle;
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adc_oneshot_unit_init_cfg_t init_config = {
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.unit_id = unit_id,
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.ulp_mode = ADC_ULP_MODE_DISABLE,
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};
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TEST_ESP_OK(adc_oneshot_new_unit(&init_config, &adc_handle));
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//-------------ADC Channel Config---------------//
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adc_oneshot_chan_cfg_t config = {
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.bitwidth = SOC_ADC_RTC_MAX_BITWIDTH,
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};
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//-------------ADC Calibration Init---------------//
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bool do_calibration = false;
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adc_cali_handle_t cali_handle[TEST_ATTEN_NUMS] = {};
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for (int i = 0; i < TEST_ATTEN_NUMS; i++) {
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do_calibration = test_adc_calibration_init(unit_id, channel, g_test_atten[i], SOC_ADC_RTC_MAX_BITWIDTH, &cali_handle[i]);
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}
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if (!do_calibration) {
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ESP_LOGW(TAG, "No efuse bits burnt, only test the regi2c analog register values");
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}
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for (int i = 0; i < TEST_ATTEN_NUMS; i++) {
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//-------------ADC Channel Config---------------//
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config.atten = g_test_atten[i];
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TEST_ESP_OK(adc_oneshot_config_channel(adc_handle, channel, &config));
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printf("Test with atten: %d\n", g_test_atten[i]);
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//---------------------------------Before Sleep-----------------------------------//
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printf("Before Light Sleep\n");
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int raw_expected = 0;
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int cali_expected = 0;
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uint8_t regi2c_cali_val_before[TEST_REGI2C_ANA_CALI_BYTE_NUM] = {};
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//Read
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TEST_ESP_OK(adc_oneshot_read(adc_handle, channel, &raw_expected));
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if (do_calibration) {
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TEST_ESP_OK(adc_cali_raw_to_voltage(cali_handle[i], raw_expected, &cali_expected));
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}
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//Print regi2c
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printf("regi2c cali val is: ");
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for (int j = 0; j < TEST_REGI2C_ANA_CALI_BYTE_NUM; j++) {
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regi2c_cali_val_before[j] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, j);
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printf("0x%x ", regi2c_cali_val_before[j]);
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}
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printf("\n");
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//Print result
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ESP_LOGI(TAG, "ADC%d Chan%d: raw data: %d", unit_id + 1, channel, raw_expected);
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ESP_LOGI(TAG, "ADC%d Chan%d: cali data: %d", unit_id + 1, channel, cali_expected);
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//---------------------------------Sleep-----------------------------------//
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esp_sleep_enable_timer_wakeup(30 * 1000);
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esp_light_sleep_start();
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//---------------------------------After Sleep-----------------------------------//
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printf("After Light Sleep\n");
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int raw_after_sleep = 0;
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int cali_after_sleep = 0;
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uint8_t regi2c_cali_val_after[TEST_REGI2C_ANA_CALI_BYTE_NUM] = {};
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//Print regi2c
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printf("regi2c cali val is: ");
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for (int i = 0; i < TEST_REGI2C_ANA_CALI_BYTE_NUM; i++) {
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regi2c_cali_val_after[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i);
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printf("0x%x ", regi2c_cali_val_after[i]);
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}
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printf("\n");
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//Read
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TEST_ESP_OK(adc_oneshot_read(adc_handle, channel, &raw_after_sleep));
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if (do_calibration) {
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TEST_ESP_OK(adc_cali_raw_to_voltage(cali_handle[i], raw_after_sleep, &cali_after_sleep));
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}
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//Print result
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ESP_LOGI(TAG, "ADC%d Chan%d: raw data: %d", unit_id + 1, channel, raw_after_sleep);
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if (do_calibration) {
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ESP_LOGI(TAG, "ADC%d Chan%d: cali data: %d", unit_id + 1, channel, cali_after_sleep);
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}
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//Compare
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int32_t raw_diff = raw_expected - raw_after_sleep;
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ESP_LOGI(TAG, "ADC%d Chan%d: raw difference: %"PRId32, unit_id + 1, channel, raw_diff);
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if (do_calibration) {
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int32_t cali_diff = cali_expected - cali_after_sleep;
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ESP_LOGI(TAG, "ADC%d Chan%d: cali difference: %"PRId32, unit_id + 1, channel, cali_diff);
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}
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//Test Calibration registers
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for (int i = 0; i < TEST_REGI2C_ANA_CALI_BYTE_NUM; i++) {
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TEST_ASSERT_EQUAL(regi2c_cali_val_before[i], regi2c_cali_val_after[i]);
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}
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ESP_LOGI(TAG, "Cali register settings unchanged");
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}
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TEST_ESP_OK(adc_oneshot_del_unit(adc_handle));
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for (int i = 0; i < TEST_ATTEN_NUMS; i++) {
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if (cali_handle[i]) {
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test_adc_calibration_deinit(cali_handle[i]);
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}
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}
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}
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//ADC Channels
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#if CONFIG_IDF_TARGET_ESP32
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#define ADC1_SLEEP_TEST_CHAN ADC_CHANNEL_6
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#define ADC2_SLEEP_TEST_CHAN ADC_CHANNEL_0
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#else
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#define ADC1_SLEEP_TEST_CHAN ADC_CHANNEL_2
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#define ADC2_SLEEP_TEST_CHAN ADC_CHANNEL_0
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#endif
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TEST_CASE("test ADC1 Single Read with Light Sleep", "[adc]")
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{
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s_adc_oneshot_with_sleep(ADC_UNIT_1, ADC1_SLEEP_TEST_CHAN);
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}
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#if (SOC_ADC_PERIPH_NUM >= 2) && !CONFIG_IDF_TARGET_ESP32C3
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//ESP32C3 ADC2 oneshot mode is not supported anymore
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TEST_CASE("test ADC2 Single Read with Light Sleep", "[adc]")
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{
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s_adc_oneshot_with_sleep(ADC_UNIT_2, ADC2_SLEEP_TEST_CHAN);
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}
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#endif //#if (SOC_ADC_PERIPH_NUM >= 2) && !CONFIG_IDF_TARGET_ESP32C3
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#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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#if SOC_ADC_MONITOR_SUPPORTED && CONFIG_SOC_ADC_DMA_SUPPORTED
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#if CONFIG_IDF_TARGET_ESP32S2
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#define TEST_ADC_FORMAT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE1
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#else
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#define TEST_ADC_FORMAT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE2
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#endif
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bool IRAM_ATTR test_high_cb(adc_monitor_handle_t monitor_handle, const adc_monitor_evt_data_t *event_data, void *user_data)
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{
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return false;
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}
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TEST_CASE("ADC continuous monitor init_deinit", "[adc]")
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{
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adc_continuous_handle_t handle = NULL;
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adc_continuous_handle_cfg_t adc_config = {
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.max_store_buf_size = 1024,
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.conv_frame_size = SOC_ADC_DIGI_DATA_BYTES_PER_CONV * 2,
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};
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TEST_ESP_OK(adc_continuous_new_handle(&adc_config, &handle));
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adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0};
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for (int i = 0; i < 1; i++) {
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adc_pattern[i].atten = ADC_ATTEN_DB_12;
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adc_pattern[i].channel = i;
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adc_pattern[i].unit = ADC_UNIT_1;
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adc_pattern[i].bit_width = SOC_ADC_DIGI_MAX_BITWIDTH;
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}
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adc_continuous_config_t dig_cfg = {
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.pattern_num = 1,
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.adc_pattern = adc_pattern,
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.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_LOW,
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.conv_mode = ADC_CONV_SINGLE_UNIT_1,
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.format = TEST_ADC_FORMAT_TYPE,
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};
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TEST_ESP_OK(adc_continuous_config(handle, &dig_cfg));
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//try to enable without installed
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adc_monitor_handle_t monitor_handle = NULL;
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TEST_ESP_ERR(ESP_ERR_INVALID_ARG, adc_continuous_monitor_enable(monitor_handle));
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//try to install with invalid argument
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adc_monitor_config_t adc_monitor_cfg = {
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.adc_unit = 2,
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.channel = 2,
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.h_threshold = 3000,
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.l_threshold = -1,
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};
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TEST_ESP_ERR(ESP_ERR_INVALID_ARG, adc_new_continuous_monitor(handle, &adc_monitor_cfg, &monitor_handle));
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//try to install when adc is running
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adc_monitor_cfg.adc_unit = ADC_UNIT_1;
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TEST_ESP_OK(adc_continuous_start(handle));
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, adc_new_continuous_monitor(handle, &adc_monitor_cfg, &monitor_handle));
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TEST_ESP_OK(adc_continuous_stop(handle));
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//normal install
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TEST_ESP_OK(adc_new_continuous_monitor(handle, &adc_monitor_cfg, &monitor_handle));
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//try register callback funcs when monitor is running
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adc_monitor_evt_cbs_t monitor_cb = {
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.on_over_high_thresh = test_high_cb,
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.on_below_low_thresh = NULL,
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};
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TEST_ESP_OK(adc_continuous_monitor_enable(monitor_handle));
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, adc_continuous_monitor_register_event_callbacks(monitor_handle, &monitor_cb, NULL));
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TEST_ESP_OK(adc_continuous_monitor_disable(monitor_handle));
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//normal register cbs
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TEST_ESP_OK(adc_continuous_monitor_register_event_callbacks(monitor_handle, &monitor_cb, NULL));
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//try init so many monitor, we totally have 2 monitors actually
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adc_monitor_handle_t monitor_handle_2 = NULL, monitor_handle_3 = NULL;
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#if CONFIG_IDF_TARGET_ESP32S2
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adc_monitor_cfg.adc_unit = ADC_UNIT_2; //s2 can't use two monitor on same ADC unit
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#endif
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TEST_ESP_OK(adc_new_continuous_monitor(handle, &adc_monitor_cfg, &monitor_handle_2));
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TEST_ESP_ERR(ESP_ERR_NOT_FOUND, adc_new_continuous_monitor(handle, &adc_monitor_cfg, &monitor_handle_3));
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//try delete them, as monitor_handle_3 should be NULL because it should init failed
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TEST_ESP_OK(adc_del_continuous_monitor(monitor_handle_2));
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TEST_ESP_ERR(ESP_ERR_INVALID_ARG, adc_del_continuous_monitor(monitor_handle_3));
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|
|
|
//try register cbs again
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, adc_continuous_monitor_register_event_callbacks(monitor_handle, &monitor_cb, &monitor_cb));
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|
|
|
//try delete it when adc is running but monitor not running
|
|
TEST_ESP_OK(adc_continuous_start(handle));
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, adc_del_continuous_monitor(monitor_handle));
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|
TEST_ESP_OK(adc_continuous_stop(handle));
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|
|
|
//normal option
|
|
TEST_ESP_OK(adc_continuous_monitor_enable(monitor_handle));
|
|
TEST_ESP_OK(adc_continuous_monitor_disable(monitor_handle));
|
|
|
|
//normal uninstall
|
|
TEST_ESP_OK(adc_del_continuous_monitor(monitor_handle));
|
|
|
|
TEST_ESP_OK(adc_continuous_deinit(handle));
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|
}
|
|
|
|
/**
|
|
* NOTE: To run this special feature test case, you need wire ADC channel pin you want to monit
|
|
* to a wave output pin defined below.
|
|
*
|
|
* +---------+
|
|
* | |
|
|
* | (adc)|------------+
|
|
* | | |
|
|
* | (wave)|------------+
|
|
* | |
|
|
* | ESP32 |
|
|
* +---------+
|
|
*
|
|
* or you can connect your signals from signal generator to ESP32 pin which you monitoring
|
|
**/
|
|
#define TEST_ADC_CHANNEL ADC_CHANNEL_0 //GPIO_1
|
|
#define TEST_WAVE_OUT_PIN GPIO_NUM_2 //GPIO_2
|
|
static uint32_t m1h_cnt, m1l_cnt;
|
|
|
|
bool IRAM_ATTR m1h_cb(adc_monitor_handle_t monitor_handle, const adc_monitor_evt_data_t *event_data, void *user_data)
|
|
{
|
|
m1h_cnt ++;
|
|
return false;
|
|
}
|
|
bool IRAM_ATTR m1l_cb(adc_monitor_handle_t monitor_handle, const adc_monitor_evt_data_t *event_data, void *user_data)
|
|
{
|
|
m1l_cnt ++;
|
|
return false;
|
|
}
|
|
TEST_CASE("ADC continuous monitor functionary", "[adc][manual][ignore]")
|
|
{
|
|
adc_continuous_handle_t handle = NULL;
|
|
adc_continuous_handle_cfg_t adc_config = {
|
|
.max_store_buf_size = 1024,
|
|
.conv_frame_size = SOC_ADC_DIGI_DATA_BYTES_PER_CONV * 2,
|
|
};
|
|
TEST_ESP_OK(adc_continuous_new_handle(&adc_config, &handle));
|
|
|
|
adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0};
|
|
for (int i = 0; i < 2; i++) {
|
|
adc_pattern[i].atten = ADC_ATTEN_DB_12;
|
|
adc_pattern[i].channel = TEST_ADC_CHANNEL;
|
|
adc_pattern[i].unit = ADC_UNIT_1;
|
|
adc_pattern[i].bit_width = SOC_ADC_DIGI_MAX_BITWIDTH;
|
|
}
|
|
adc_continuous_config_t dig_cfg = {
|
|
.pattern_num = 2,
|
|
.adc_pattern = adc_pattern,
|
|
.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_LOW,
|
|
.conv_mode = ADC_CONV_SINGLE_UNIT_1,
|
|
.format = TEST_ADC_FORMAT_TYPE,
|
|
};
|
|
TEST_ESP_OK(adc_continuous_config(handle, &dig_cfg));
|
|
|
|
//config monitor
|
|
adc_monitor_handle_t monitor_handle;
|
|
adc_monitor_config_t adc_monitor_cfg = {
|
|
.adc_unit = ADC_UNIT_1,
|
|
.channel = TEST_ADC_CHANNEL,
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
|
.h_threshold = -1, //S2 support only one threshold for one monitor
|
|
#else
|
|
.h_threshold = 3000,
|
|
#endif
|
|
.l_threshold = 1000,
|
|
};
|
|
adc_monitor_evt_cbs_t monitor_cb = {
|
|
#if !CONFIG_IDF_TARGET_ESP32S2
|
|
.on_over_high_thresh = m1h_cb,
|
|
#endif
|
|
.on_below_low_thresh = m1l_cb,
|
|
};
|
|
TEST_ESP_OK(adc_new_continuous_monitor(handle, &adc_monitor_cfg, &monitor_handle));
|
|
TEST_ESP_OK(adc_continuous_monitor_register_event_callbacks(monitor_handle, &monitor_cb, NULL));
|
|
|
|
//config a pin to generate wave
|
|
gpio_config_t gpio_cfg = {
|
|
.pin_bit_mask = (1ULL << TEST_WAVE_OUT_PIN),
|
|
.mode = GPIO_MODE_INPUT_OUTPUT,
|
|
.pull_up_en = GPIO_PULLDOWN_ENABLE,
|
|
};
|
|
TEST_ESP_OK(gpio_config(&gpio_cfg));
|
|
|
|
TEST_ESP_OK(adc_continuous_monitor_enable(monitor_handle));
|
|
TEST_ESP_OK(adc_continuous_start(handle));
|
|
|
|
for (uint8_t i = 0; i < 8; i++) {
|
|
vTaskDelay(1000);
|
|
|
|
// check monitor cb
|
|
printf("%d\t high_cnt %4ld\tlow_cnt %4ld\n", i, m1h_cnt, m1l_cnt);
|
|
if (gpio_get_level(TEST_WAVE_OUT_PIN)) {
|
|
#if !CONFIG_IDF_TARGET_ESP32S2
|
|
// TEST_ASSERT_UINT32_WITHIN(SOC_ADC_SAMPLE_FREQ_THRES_LOW*0.1, SOC_ADC_SAMPLE_FREQ_THRES_LOW, m1h_cnt);
|
|
// TEST_ASSERT_LESS_THAN_UINT32(5, m1l_cnt); //Actually, it will still encountered 1~2 times because hardware run very quickly
|
|
#endif
|
|
m1h_cnt = 0;
|
|
gpio_set_level(TEST_WAVE_OUT_PIN, 0);
|
|
} else {
|
|
TEST_ASSERT_UINT32_WITHIN(SOC_ADC_SAMPLE_FREQ_THRES_LOW * 0.1, SOC_ADC_SAMPLE_FREQ_THRES_LOW, m1l_cnt);
|
|
TEST_ASSERT_LESS_THAN_UINT32(5, m1h_cnt); //Actually, it will still encountered 1~2 times because hardware run very quickly
|
|
m1l_cnt = 0;
|
|
gpio_set_level(TEST_WAVE_OUT_PIN, 1);
|
|
}
|
|
}
|
|
TEST_ESP_OK(adc_continuous_stop(handle));
|
|
TEST_ESP_OK(adc_continuous_monitor_disable(monitor_handle));
|
|
TEST_ESP_OK(adc_del_continuous_monitor(monitor_handle));
|
|
TEST_ESP_OK(adc_continuous_deinit(handle));
|
|
}
|
|
|
|
#endif //SOC_ADC_MONITOR_SUPPORTED && CONFIG_SOC_ADC_DMA_SUPPORTED
|