mirror of
https://github.com/espressif/esp-idf.git
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295 lines
13 KiB
C
295 lines
13 KiB
C
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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typedef volatile struct {
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uint32_t reserved_0;
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uint32_t reserved_4;
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uint32_t reserved_8;
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uint32_t reserved_c;
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uint32_t reserved_10;
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uint32_t reserved_14;
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uint32_t reserved_18;
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uint32_t reserved_1c;
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uint32_t reserved_20;
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uint32_t reserved_24;
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uint32_t reserved_28;
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uint32_t reserved_2c;
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uint32_t reserved_30;
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uint32_t reserved_34;
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uint32_t reserved_38;
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uint32_t reserved_3c;
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uint32_t reserved_40;
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uint32_t reserved_44;
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uint32_t reserved_48;
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uint32_t reserved_4c;
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uint32_t reserved_50;
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uint32_t reserved_54;
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uint32_t reserved_58;
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uint32_t reserved_5c;
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uint32_t reserved_60;
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uint32_t reserved_64;
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uint32_t reserved_68;
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uint32_t reserved_6c;
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uint32_t reserved_70;
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uint32_t reserved_74;
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uint32_t reserved_78;
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uint32_t reserved_7c;
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uint32_t reserved_80;
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uint32_t reserved_84;
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uint32_t reserved_88;
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uint32_t reserved_8c;
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uint32_t reserved_90;
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uint32_t reserved_94;
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uint32_t reserved_98;
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uint32_t reserved_9c;
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uint32_t reserved_a0;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t reserved_fc;
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uint32_t reserved_100;
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uint32_t reserved_104;
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uint32_t reserved_108;
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uint32_t reserved_10c;
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uint32_t reserved_110;
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uint32_t reserved_114;
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uint32_t reserved_118;
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uint32_t reserved_11c;
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uint32_t reserved_120;
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uint32_t reserved_124;
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uint32_t reserved_128;
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uint32_t reserved_12c;
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uint32_t reserved_130;
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uint32_t reserved_134;
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uint32_t reserved_138;
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uint32_t reserved_13c;
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uint32_t reserved_140;
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uint32_t reserved_144;
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uint32_t reserved_148;
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uint32_t reserved_14c;
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uint32_t reserved_150;
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uint32_t reserved_154;
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uint32_t reserved_158;
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uint32_t reserved_15c;
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uint32_t reserved_160;
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uint32_t reserved_164;
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uint32_t reserved_168;
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uint32_t reserved_16c;
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uint32_t reserved_170;
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uint32_t reserved_174;
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uint32_t reserved_178;
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uint32_t reserved_17c;
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uint32_t reserved_180;
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uint32_t reserved_184;
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uint32_t reserved_188;
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uint32_t reserved_18c;
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uint32_t reserved_190;
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uint32_t reserved_194;
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uint32_t reserved_198;
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uint32_t reserved_19c;
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uint32_t reserved_1a0;
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uint32_t reserved_1a4;
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uint32_t reserved_1a8;
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uint32_t reserved_1ac;
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uint32_t reserved_1b0;
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uint32_t reserved_1b4;
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uint32_t reserved_1b8;
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uint32_t reserved_1bc;
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union {
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struct {
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uint32_t rd_mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
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uint32_t rd_sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
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uint32_t rd_usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
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uint32_t rd_key0_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
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uint32_t rd_key1_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
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uint32_t rd_key2_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
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uint32_t rd_key3_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
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uint32_t rd_key4_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
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};
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uint32_t val;
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} rd_rs_err0;
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union {
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struct {
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uint32_t rd_key5_err_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
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uint32_t rd_sys_part2_num: 3; /*The value of this signal means the number of error bytes.*/
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uint32_t rd_sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
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uint32_t reserved8: 24; /*Reserved.*/
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};
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uint32_t val;
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} rd_rs_err1;
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union {
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struct {
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uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/
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uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/
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uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/
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uint32_t reserved3: 13; /*Reserved.*/
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uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/
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uint32_t reserved17: 15; /*Reserved.*/
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};
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uint32_t val;
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} clk;
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union {
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struct {
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uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
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uint32_t reserved16: 16; /*Reserved.*/
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};
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uint32_t val;
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} conf;
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union {
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struct {
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uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/
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uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/
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uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/
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uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/
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uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/
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uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/
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uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/
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uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/
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uint32_t reserved18: 14; /*Reserved.*/
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};
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uint32_t val;
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} status;
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union {
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struct {
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uint32_t read_cmd: 1; /*Set this bit to send read command.*/
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uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/
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uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/
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uint32_t reserved6: 26; /*Reserved.*/
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};
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uint32_t val;
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} cmd;
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union {
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struct {
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uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/
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uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/
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uint32_t reserved2: 30; /*Reserved.*/
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t read_done: 1; /*The status signal for read_done interrupt.*/
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uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/
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uint32_t reserved2: 30; /*Reserved.*/
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/
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uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/
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uint32_t reserved2: 30; /*Reserved.*/
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/
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uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/
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uint32_t reserved2: 30; /*Reserved.*/
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/
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uint32_t dac_clk_pad_sel: 1; /*Don't care.*/
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uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/
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uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/
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uint32_t reserved18: 14; /*Reserved.*/
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};
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uint32_t val;
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} dac_conf;
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union {
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struct {
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uint32_t thr_a: 8; /*Configures the hold time of read operation.*/
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uint32_t trd: 8; /*Configures the length of pulse of read operation.*/
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uint32_t tsur_a: 8; /*Configures the setup time of read operation.*/
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uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/
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};
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uint32_t val;
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} rd_tim_conf;
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union {
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struct {
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uint32_t thp_a: 8; /*Configures the hold time of programming operation.*/
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uint32_t tpgm_inactive: 8; /*Configures the length of pulse during programming 0 to eFuse.*/
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uint32_t tpgm: 16; /*Configures the length of pulse during programming 1 to eFuse.*/
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};
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uint32_t val;
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} wr_tim_conf0;
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union {
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struct {
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uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/
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uint32_t pwr_on_num: 16; /*Configures the power up time for VDDQ.*/
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uint32_t reserved24: 8; /*Reserved.*/
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};
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uint32_t val;
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} wr_tim_conf1;
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union {
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struct {
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uint32_t pwr_off_num: 16; /*Configures the power outage time for VDDQ.*/
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uint32_t reserved16: 16; /*Reserved.*/
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};
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uint32_t val;
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} wr_tim_conf2;
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union {
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struct {
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uint32_t date: 28; /*Stores eFuse version.*/
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uint32_t reserved28: 4; /*Reserved.*/
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};
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uint32_t val;
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} date;
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} efuse_dev_t;
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extern efuse_dev_t EFUSE;
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#ifdef __cplusplus
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}
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#endif
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