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b23c9142d5
* Functions for setting and clearing interrupts as well as function to read interrupt mask should be clearer now. * Using hal layer interrupt set and clear functions in esp_wifi component
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/soc.h"
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#include "xtensa/xtensa_api.h"
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#include "xtensa/config/specreg.h"
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#include "xt_instr_macros.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief enable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be enabled
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*/
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static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask)
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{
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xt_ints_on(mask);
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}
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/**
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* @brief disable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be disabled
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*/
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static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
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{
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xt_ints_off(mask);
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}
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/**
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* @brief Read the current interrupt mask of the CPU running this code.
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*
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* @return The current interrupt bitmask.
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*/
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static inline uint32_t intr_cntrl_ll_read_interrupt_mask(void)
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{
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uint32_t int_mask;
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RSR(INTENABLE, int_mask);
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return int_mask;
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}
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/**
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* @brief checks if given interrupt number has a valid handler
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
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* @return true for valid handler, false otherwise
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*/
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static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
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{
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return xt_int_has_handler(intr, cpu);
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}
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/**
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* @brief sets interrupt handler and optional argument of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param handler handler invoked when an interrupt occurs
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* @param arg optional argument to pass to the handler
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*/
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static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
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{
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xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
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}
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/**
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* @brief Gets argument passed to handler of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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*
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* @return argument used by handler of passed interrupt number
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*/
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static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
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{
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return xt_get_interrupt_handler_arg(intr);
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}
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/**
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* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
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*
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* @param intr interrupt number ranged from 0 to 31
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*/
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static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
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{
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xthal_set_intclear(1 << intr);
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}
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#ifdef __cplusplus
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}
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#endif
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