esp-idf/components/driver/Kconfig
morris 9b6d4c4015
uart: support alloc driver object in SRAM
If CONFIG_UART_ISR_IN_IRAM is on, which means user hope the uart
interrupt can still be serviced even when cache is diabled (e.g.
writing to flash). In that case, the driver should make sure to
put the all related objects into SRAM, avoid putting them in the PSRAM.

Closes https://github.com/espressif/esp-idf/issues/7044
Closes https://github.com/espressif/esp-idf/pull/7355
2021-09-22 12:01:04 +08:00

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menu "Driver configurations"
menu "ADC configuration"
config ADC_FORCE_XPD_FSM
bool "Use the FSM to control ADC power"
default n
help
ADC power can be controlled by the FSM instead of software. This allows the ADC to
be shut off when it is not working leading to lower power consumption. However
using the FSM control ADC power will increase the noise of ADC.
config ADC_DISABLE_DAC
bool "Disable DAC when ADC2 is used on GPIO 25 and 26"
default y
help
If this is set, the ADC2 driver will disable the output of the DAC corresponding to the specified
channel. This is the default value.
For testing, disable this option so that we can measure the output of DAC by internal ADC.
endmenu # ADC Configuration
menu "SPI configuration"
config SPI_MASTER_IN_IRAM
bool "Place transmitting functions of SPI master into IRAM"
default n
select SPI_MASTER_ISR_IN_IRAM
help
Normally only the ISR of SPI master is placed in the IRAM, so that it
can work without the flash when interrupt is triggered.
For other functions, there's some possibility that the flash cache
miss when running inside and out of SPI functions, which may increase
the interval of SPI transactions.
Enable this to put ``queue_trans``, ``get_trans_result`` and
``transmit`` functions into the IRAM to avoid possible cache miss.
During unit test, this is enabled to measure the ideal case of api.
config SPI_MASTER_ISR_IN_IRAM
bool "Place SPI master ISR function into IRAM"
default y
help
Place the SPI master ISR in to IRAM to avoid possible cache miss.
Also you can forbid the ISR being disabled during flash writing
access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
config SPI_SLAVE_IN_IRAM
bool "Place transmitting functions of SPI slave into IRAM"
default n
select SPI_SLAVE_ISR_IN_IRAM
help
Normally only the ISR of SPI slave is placed in the IRAM, so that it
can work without the flash when interrupt is triggered.
For other functions, there's some possibility that the flash cache
miss when running inside and out of SPI functions, which may increase
the interval of SPI transactions.
Enable this to put ``queue_trans``, ``get_trans_result`` and
``transmit`` functions into the IRAM to avoid possible cache miss.
config SPI_SLAVE_ISR_IN_IRAM
bool "Place SPI slave ISR function into IRAM"
default y
help
Place the SPI slave ISR in to IRAM to avoid possible cache miss.
Also you can forbid the ISR being disabled during flash writing
access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
endmenu # SPI Configuration
menu "TWAI configuration"
config TWAI_ISR_IN_IRAM
bool "Place TWAI ISR function into IRAM"
default n
select FREERTOS_SUPPORT_STATIC_ALLOCATION
# We need to enable FREERTOS_SUPPORT_STATIC_ALLOCATION because the
# TWAI driver requires the use of FreeRTOS Queues and Semaphores from
# the driver ISR. These Queues and Semaphores need to be placed in
# DRAM thus FreeRTOS static allocation API is required.
help
Place the TWAI ISR in to IRAM. This will allow the ISR to avoid
cache misses, and also be able to run whilst the cache is disabled
(such as when writing to SPI Flash).
Note that if this option is enabled:
- Users should also set the ESP_INTR_FLAG_IRAM in the driver
configuration structure when installing the driver (see docs for
specifics).
- Alert logging (i.e., setting of the TWAI_ALERT_AND_LOG flag)
will have no effect.
endmenu # TWAI Configuration
menu "UART configuration"
config UART_ISR_IN_IRAM
bool "Place UART ISR function into IRAM"
default n
select FREERTOS_SUPPORT_STATIC_ALLOCATION
help
If this option is not selected, UART interrupt will be disabled for a long time and
may cause data lost when doing spi flash operation.
endmenu # UART Configuration
menu "RTCIO configuration"
visible if IDF_TARGET_ESP32
config RTCIO_SUPPORT_RTC_GPIO_DESC
bool "Support array `rtc_gpio_desc` for ESP32"
depends on IDF_TARGET_ESP32
default n
help
The the array `rtc_gpio_desc` will don't compile by default.
If this option is selected, the array `rtc_gpio_desc` can be compile.
If user use this array, please enable this configuration.
endmenu # RTCIO Configuration
endmenu # Driver configurations