mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-21 06:56:11 -04:00
ae2da1e235
Resolved possible race conditions when accessing registers in different banks. Added Tx ready semaphore when requesting packet to transmit (ENC is slow => access to it needs to be controlled). Added setting of CS hold time based on Data sheet. Added option to set the ENC28J60 to Full Duplex mode. Addressed several ENC28J60 Erratas. Restructured ENC28J60 example folder structure so the driver could be easily linked from different projects. Extended the README to guide users of how to properly use the ENC28J60 chip. Extended iperf example to include ENC28J60. Closes https://github.com/espressif/esp-idf/issues/4747 Closes https://github.com/espressif/esp-idf/issues/7117 Closes https://github.com/espressif/esp-idf/issues/7156
239 lines
12 KiB
C
239 lines
12 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief SPI Instruction Set
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*
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*/
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#define ENC28J60_SPI_CMD_RCR (0x00) // Read Control Register
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#define ENC28J60_SPI_CMD_RBM (0x01) // Read Buffer Memory
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#define ENC28J60_SPI_CMD_WCR (0x02) // Write Control Register
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#define ENC28J60_SPI_CMD_WBM (0x03) // Write Buffer Memory
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#define ENC28J60_SPI_CMD_BFS (0x04) // Bit Field Set
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#define ENC28J60_SPI_CMD_BFC (0x05) // Bit Field Clear
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#define ENC28J60_SPI_CMD_SRC (0x07) // Soft Reset
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/**
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* @brief Shared Registers in ENC28J60 (accessible on each bank)
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*
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*/
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#define ENC28J60_EIE (0x1B) // Ethernet Interrupt Enable
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#define ENC28J60_EIR (0x1C) // Ethernet Interrupt flags
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#define ENC28J60_ESTAT (0x1D) // Ethernet Status
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#define ENC28J60_ECON2 (0x1E) // Ethernet Control Register2
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#define ENC28J60_ECON1 (0x1F) // Ethernet Control Register1
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/**
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* @brief Per-bank Registers in ENC28J60
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* @note Address[15:12]: Register Type, 0 -> ETH, 1 -> MII/MAC
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* Address[11:8] : Bank address
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* Address[7:0] : Register Index
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*/
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// Bank 0 Registers
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#define ENC28J60_ERDPTL (0x0000) // Read Pointer Low Byte ERDPT<7:0>)
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#define ENC28J60_ERDPTH (0x0001) // Read Pointer High Byte (ERDPT<12:8>)
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#define ENC28J60_EWRPTL (0x0002) // Write Pointer Low Byte (EWRPT<7:0>)
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#define ENC28J60_EWRPTH (0x0003) // Write Pointer High Byte (EWRPT<12:8>)
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#define ENC28J60_ETXSTL (0x0004) // TX Start Low Byte (ETXST<7:0>)
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#define ENC28J60_ETXSTH (0x0005) // TX Start High Byte (ETXST<12:8>)
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#define ENC28J60_ETXNDL (0x0006) // TX End Low Byte (ETXND<7:0>)
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#define ENC28J60_ETXNDH (0x0007) // TX End High Byte (ETXND<12:8>)
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#define ENC28J60_ERXSTL (0x0008) // RX Start Low Byte (ERXST<7:0>)
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#define ENC28J60_ERXSTH (0x0009) // RX Start High Byte (ERXST<12:8>)
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#define ENC28J60_ERXNDL (0x000A) // RX End Low Byte (ERXND<7:0>)
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#define ENC28J60_ERXNDH (0x000B) // RX End High Byte (ERXND<12:8>)
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#define ENC28J60_ERXRDPTL (0x000C) // RX RD Pointer Low Byte (ERXRDPT<7:0>)
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#define ENC28J60_ERXRDPTH (0x000D) // RX RD Pointer High Byte (ERXRDPT<12:8>)
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#define ENC28J60_ERXWRPTL (0x000E) // RX WR Pointer Low Byte (ERXWRPT<7:0>)
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#define ENC28J60_ERXWRPTH (0x000F) // RX WR Pointer High Byte (ERXWRPT<12:8>)
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#define ENC28J60_EDMASTL (0x0010) // DMA Start Low Byte (EDMAST<7:0>)
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#define ENC28J60_EDMASTH (0x0011) // DMA Start High Byte (EDMAST<12:8>)
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#define ENC28J60_EDMANDL (0x0012) // DMA End Low Byte (EDMAND<7:0>)
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#define ENC28J60_EDMANDH (0x0013) // DMA End High Byte (EDMAND<12:8>)
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#define ENC28J60_EDMADSTL (0x0014) // DMA Destination Low Byte (EDMADST<7:0>)
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#define ENC28J60_EDMADSTH (0x0015) // DMA Destination High Byte (EDMADST<12:8>)
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#define ENC28J60_EDMACSL (0x0016) // DMA Checksum Low Byte (EDMACS<7:0>)
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#define ENC28J60_EDMACSH (0x0017) // DMA Checksum High Byte (EDMACS<15:8>)
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// Bank 1 Registers
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#define ENC28J60_EHT0 (0x0100) // Hash Table Byte 0 (EHT<7:0>)
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#define ENC28J60_EHT1 (0x0101) // Hash Table Byte 1 (EHT<15:8>)
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#define ENC28J60_EHT2 (0x0102) // Hash Table Byte 2 (EHT<23:16>)
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#define ENC28J60_EHT3 (0x0103) // Hash Table Byte 3 (EHT<31:24>)
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#define ENC28J60_EHT4 (0x0104) // Hash Table Byte 4 (EHT<39:32>)
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#define ENC28J60_EHT5 (0x0105) // Hash Table Byte 5 (EHT<47:40>)
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#define ENC28J60_EHT6 (0x0106) // Hash Table Byte 6 (EHT<55:48>)
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#define ENC28J60_EHT7 (0x0107) // Hash Table Byte 7 (EHT<63:56>)
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#define ENC28J60_EPMM0 (0x0108) // Pattern Match Mask Byte 0 (EPMM<7:0>)
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#define ENC28J60_EPMM1 (0x0109) // Pattern Match Mask Byte 1 (EPMM<15:8>)
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#define ENC28J60_EPMM2 (0x010A) // Pattern Match Mask Byte 2 (EPMM<23:16>)
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#define ENC28J60_EPMM3 (0x010B) // Pattern Match Mask Byte 3 (EPMM<31:24>)
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#define ENC28J60_EPMM4 (0x010C) // Pattern Match Mask Byte 4 (EPMM<39:32>)
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#define ENC28J60_EPMM5 (0x010D) // Pattern Match Mask Byte 5 (EPMM<47:40>)
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#define ENC28J60_EPMM6 (0x010E) // Pattern Match Mask Byte 6 (EPMM<55:48>)
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#define ENC28J60_EPMM7 (0x010F) // Pattern Match Mask Byte 7 (EPMM<63:56>)
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#define ENC28J60_EPMCSL (0x0110) // Pattern Match Checksum Low Byte (EPMCS<7:0>)
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#define ENC28J60_EPMCSH (0x0111) // Pattern Match Checksum High Byte (EPMCS<15:0>)
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#define ENC28J60_EPMOL (0x0114) // Pattern Match Offset Low Byte (EPMO<7:0>)
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#define ENC28J60_EPMOH (0x0115) // Pattern Match Offset High Byte (EPMO<12:8>)
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#define ENC28J60_ERXFCON (0x0118) // Receive Fileter Control
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#define ENC28J60_EPKTCNT (0x0119) // Ethernet Packet Count
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// Bank 2 Register
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#define ENC28J60_MACON1 (0x1200) // MAC Control Register 1
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#define ENC28J60_MACON2 (0x1201) // MAC Control Register 2
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#define ENC28J60_MACON3 (0x1202) // MAC Control Register 3
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#define ENC28J60_MACON4 (0x1203) // MAC Control Register 4
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#define ENC28J60_MABBIPG (0x1204) // Back-to-Back Inter-Packet Gap (BBIPG<6:0>)
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#define ENC28J60_MAIPGL (0x1206) // Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>)
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#define ENC28J60_MAIPGH (0x1207) // Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>)
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#define ENC28J60_MACLCON1 (0x1208) // Retransmission Maximum (RETMAX<3:0>)
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#define ENC28J60_MACLCON2 (0x1209) // Collision Window (COLWIN<5:0>)
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#define ENC28J60_MAMXFLL (0x120A) // Maximum Frame Length Low Byte (MAMXFL<7:0>)
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#define ENC28J60_MAMXFLH (0x120B) // Maximum Frame Length High Byte (MAMXFL<15:8>)
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#define ENC28J60_MICMD (0x1212) // MII Command Register
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#define ENC28J60_MIREGADR (0x1214) // MII Register Address (MIREGADR<4:0>)
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#define ENC28J60_MIWRL (0x1216) // MII Write Data Low Byte (MIWR<7:0>)
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#define ENC28J60_MIWRH (0x1217) // MII Write Data High Byte (MIWR<15:8>)
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#define ENC28J60_MIRDL (0x1218) // MII Read Data Low Byte (MIRD<7:0>)
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#define ENC28J60_MIRDH (0x1219) // MII Read Data High Byte(MIRD<15:8>)
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// Bank 3 Registers
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#define ENC28J60_MAADR5 (0x1300) // MAC Address Byte 5 (MAADR<15:8>)
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#define ENC28J60_MAADR6 (0x1301) // MAC Address Byte 6 (MAADR<7:0>)
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#define ENC28J60_MAADR3 (0x1302) // MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3
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#define ENC28J60_MAADR4 (0x1303) // MAC Address Byte 4 (MAADR<23:16>)
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#define ENC28J60_MAADR1 (0x1304) // MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1
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#define ENC28J60_MAADR2 (0x1305) // MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2
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#define ENC28J60_EBSTSD (0x0306) // Built-in Self-Test Fill Seed (EBSTSD<7:0>)
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#define ENC28J60_EBSTCON (0x0307) // Built-in Self-Test Control
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#define ENC28J60_EBSTCSL (0x0308) // Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>)
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#define ENC28J60_EBSTCSH (0x0309) // Built-in Self-Test Checksum High Byte (EBSTCS<15:8>)
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#define ENC28J60_MISTAT (0x130A) // MII Status Register
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#define ENC28J60_EREVID (0x0312) // Ethernet Revision ID (EREVID<4:0>)
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#define ENC28J60_ECOCON (0x0315) // Clock Output Control Register
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#define ENC28J60_EFLOCON (0x0317) // Ethernet Flow Control
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#define ENC28J60_EPAUSL (0x0318) // Pause Timer Value Low Byte (EPAUS<7:0>)
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#define ENC28J60_EPAUSH (0x0319) // Pause Timer Value High Byte (EPAUS<15:8>)
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/**
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* @brief status and flag of ENC28J60 specific registers
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*
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*/
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// EIE bit definitions
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#define EIE_INTIE (1<<7) // Global INT Interrupt Enable
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#define EIE_PKTIE (1<<6) // Receive Packet Pending Interrupt Enable
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#define EIE_DMAIE (1<<5) // DMA Interrupt Enable
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#define EIE_LINKIE (1<<4) // Link Status Change Interrupt Enable
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#define EIE_TXIE (1<<3) // Transmit Enable
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#define EIE_TXERIE (1<<1) // Transmit Error Interrupt Enable
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#define EIE_RXERIE (1<<0) // Receive Error Interrupt Enable
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// EIR bit definitions
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#define EIR_PKTIF (1<<6) // Receive Packet Pending Interrupt Flag
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#define EIR_DMAIF (1<<5) // DMA Interrupt Flag
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#define EIR_LINKIF (1<<4) // Link Change Interrupt Flag
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#define EIR_TXIF (1<<3) // Transmit Interrupt Flag
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#define EIR_TXERIF (1<<1) // Transmit Error Interrupt Flag
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#define EIR_RXERIF (1<<0) // Receive Error Interrupt Flag
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// ESTAT bit definitions
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#define ESTAT_INT (1<<7) // INT Interrupt Flag
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#define ESTAT_BUFER (1<<6) // Buffer Error Status
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#define ESTAT_LATECOL (1<<4) // Late Collision Error
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#define ESTAT_RXBUSY (1<<2) // Receive Busy
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#define ESTAT_TXABRT (1<<1) // Transmit Abort Error
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#define ESTAT_CLKRDY (1<<0) // Clock Ready
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// ECON2 bit definitions
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#define ECON2_AUTOINC (1<<7) // Automatic Buffer Pointer Increment Enable
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#define ECON2_PKTDEC (1<<6) // Packet Decrement
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#define ECON2_PWRSV (1<<5) // Power Save Enable
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#define ECON2_VRPS (1<<3) // Voltage Regulator Power Save Enable
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// ECON1 bit definitions
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#define ECON1_TXRST (1<<7) // Transmit Logic Reset
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#define ECON1_RXRST (1<<6) // Receive Logic Reset
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#define ECON1_DMAST (1<<5) // DMA Start and Busy Status
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#define ECON1_CSUMEN (1<<4) // DMA Checksum Enable
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#define ECON1_TXRTS (1<<3) // Transmit Request to Send
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#define ECON1_RXEN (1<<2) // Receive Enable
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#define ECON1_BSEL1 (1<<1) // Bank Select1
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#define ECON1_BSEL0 (1<<0) // Bank Select0
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// ERXFCON bit definitions
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#define ERXFCON_UCEN (1<<7) // Unicast Filter Enable
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#define ERXFCON_ANDOR (1<<6) // AND/OR Filter Select
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#define ERXFCON_CRCEN (1<<5) // Post-Filter CRC Check Enable
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#define ERXFCON_PMEN (1<<4) // Pattern Match Filter Enable
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#define ERXFCON_MPEN (1<<3) // Magic Packet Filter Enable
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#define ERXFCON_HTEN (1<<2) // Hash Table Filter Enable
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#define ERXFCON_MCEN (1<<1) // Multicast Filter Enable
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#define ERXFCON_BCEN (1<<0) // Broadcast Filter Enable
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// MACON1 bit definitions
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#define MACON1_TXPAUS (1<<3) // Pause Control Frame Transmission Enable
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#define MACON1_RXPAUS (1<<2) // Pause Control Frame Reception Enable
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#define MACON1_PASSALL (1<<1) // Pass All Received Frames Enable
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#define MACON1_MARXEN (1<<0) // MAC Receive Enable
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// MACON3 bit definitions
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#define MACON3_PADCFG2 (1<<7) // Automatic Pad and CRC Configuration bit 2
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#define MACON3_PADCFG1 (1<<6) // Automatic Pad and CRC Configuration bit 1
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#define MACON3_PADCFG0 (1<<5) // Automatic Pad and CRC Configuration bit 0
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#define MACON3_TXCRCEN (1<<4) // Transmit CRC Enable
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#define MACON3_PHDRLEN (1<<3) // Proprietary Header Enable
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#define MACON3_HFRMLEN (1<<2) // Huge Frame Enable
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#define MACON3_FRMLNEN (1<<1) // Frame Length Checking Enable
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#define MACON3_FULDPX (1<<0) // MAC Full-Duplex Enable
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// MACON4 bit definitions
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#define MACON4_DEFER (1<<6) // Defer Transmission Enable
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#define MACON4_BPEN (1<<5) // No Backoff During Backpressure Enable
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#define MACON4_NOBKFF (1<<4) // No Backoff Enable
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// MICMD bit definitions
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#define MICMD_MIISCAN (1<<1) // MII Scan Enable
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#define MICMD_MIIRD (1<<0) // MII Read Enable
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// EBSTCON bit definitions
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#define EBSTCON_PSV2 (1<<7) // Pattern Shift Value 2
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#define EBSTCON_PSV1 (1<<6) // Pattern Shift Value 1
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#define EBSTCON_PSV0 (1<<5) // Pattern Shift Value 0
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#define EBSTCON_PSEL (1<<4) // Port Select
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#define EBSTCON_TMSEL1 (1<<3) // Test Mode Select 1
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#define EBSTCON_TMSEL0 (1<<2) // Test Mode Select 0
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#define EBSTCON_TME (1<<1) // Test Mode Enable
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#define EBSTCON_BISTST (1<<0) // Built-in Self-Test Start/Busy
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// MISTAT bit definitions
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#define MISTAT_NVALID (1<<2) // MII Management Read Data Not Valid
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#define MISTAT_SCAN (1<<1) // MII Management Scan Operation in Progress
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#define MISTAT_BUSY (1<<0) // MII Management Busy
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// EFLOCON bit definitions
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#define EFLOCON_FULDPXS (1<<2) // Full-Duplex Shadown
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#define EFLOCON_FCEN1 (1<<1) // Flow Control Enable 1
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#define EFLOCON_FCEN0 (1<<0) // Flow Control Enable 0
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#ifdef __cplusplus
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}
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#endif
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