mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-20 00:36:01 -04:00
12325ff47e
1. mem_burst_length register field correction 2. remove dma buffer addr range restriction 3. M2M periph sel ID no need to be identical for TX and RX channels 4. correct rx descriptor owner field auto clear 5. remove fsm idle assertion for ERR_EOF
95 lines
4.5 KiB
C
95 lines
4.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <sys/queue.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_intr_alloc.h"
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#include "esp_heap_caps.h"
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#include "soc/soc_caps.h"
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#include "hal/dma2d_hal.h"
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#include "hal/dma2d_ll.h"
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#include "esp_private/dma2d.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if CONFIG_DMA2D_OPERATION_FUNC_IN_IRAM || CONFIG_DMA2D_ISR_IRAM_SAFE
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#define DMA2D_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define DMA2D_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
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#endif
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#if CONFIG_DMA2D_ISR_IRAM_SAFE
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#define DMA2D_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_IRAM)
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#else
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#define DMA2D_INTR_ALLOC_FLAGS ESP_INTR_FLAG_SHARED
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#endif
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#define DMA2D_RX_DEFAULT_INTR_FLAG (DMA2D_LL_EVENT_RX_SUC_EOF | DMA2D_LL_EVENT_RX_ERR_EOF | DMA2D_LL_EVENT_RX_DESC_ERROR)
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typedef struct dma2d_channel_t dma2d_channel_t;
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typedef struct dma2d_tx_channel_t dma2d_tx_channel_t;
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typedef struct dma2d_rx_channel_t dma2d_rx_channel_t;
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typedef struct dma2d_group_t dma2d_group_t;
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struct dma2d_trans_s {
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TAILQ_ENTRY(dma2d_trans_s) entry; // Link entry
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const dma2d_trans_config_t *desc; // Pointer to the structure containing all configuration items of a transaction
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dma2d_channel_handle_t rx_chan; // Pointer to the RX channel handle that will be used to do the transaction
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};
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struct dma2d_group_t {
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int group_id; // Group ID, index from 0
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dma2d_hal_context_t hal; // HAL instance is at group level
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portMUX_TYPE spinlock; // Group level spinlock
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TAILQ_HEAD(pending_trans, dma2d_trans_s) pending_trans_tailq; // Link head of pending 2D-DMA transactions
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uint8_t tx_channel_free_mask; // Bit mask indicating the free TX channels at the moment
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uint8_t rx_channel_free_mask; // Bit mask indicating the free RX channels at the moment
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uint8_t tx_channel_reserved_mask; // Bit mask indicating the being reserved TX channels
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uint8_t rx_channel_reserved_mask; // Bit mask indicating the being reserved RX channels
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uint32_t tx_periph_m2m_free_id_mask; // Bit mask indicating the available TX M2M peripheral selelction IDs at the moment
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uint32_t rx_periph_m2m_free_id_mask; // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment
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dma2d_tx_channel_t *tx_chans[SOC_DMA2D_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels
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dma2d_rx_channel_t *rx_chans[SOC_DMA2D_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels
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int intr_priority; // All channels in the same group should share the same interrupt priority
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};
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struct dma2d_channel_t {
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dma2d_group_t *group; // Which group the channel belongs to
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int channel_id; // Channel ID
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dma2d_channel_direction_t direction; // Channel direction, TX or RX
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intr_handle_t intr; // Per-channel interrupt handle
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portMUX_TYPE spinlock; // Channel level spinlock
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struct {
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dma2d_trans_t *transaction; // Pointer to the 2D-DMA transaction context that is currently being processed on the channel
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uint32_t reorder_en : 1; // This flag indicates the channel will enable reorder functionality
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int periph_sel_id : (DMA2D_LL_CHANNEL_PERIPH_SEL_BIT_WIDTH + 1); // This is used to record the periph_sel_id of each channel
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} status;
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};
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struct dma2d_tx_channel_t {
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dma2d_channel_t base; // 2D-DMA channel base class
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void *user_data; // User registered DMA event data
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dma2d_event_callback_t on_desc_done; // TX DONE event callback
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};
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struct dma2d_rx_channel_t {
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dma2d_channel_t base; // 2D-DMA channel base class
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void *user_data; // User registered DMA event data
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dma2d_event_callback_t on_recv_eof; // RX EOF event callback
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dma2d_event_callback_t on_desc_done; // RX DONE event callback
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uint32_t bundled_tx_channel_mask; // Bit mask indicating the TX channels together with the RX channel to do the transaction
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};
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#ifdef __cplusplus
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}
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#endif
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