mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
315 lines
11 KiB
C
315 lines
11 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_RMT_STRUCT_H_
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#define _SOC_RMT_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct rmt_dev_s {
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uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */
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struct {
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union {
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struct {
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uint32_t div_cnt: 8;
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uint32_t idle_thres: 16;
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uint32_t mem_size: 3;
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uint32_t carrier_eff_en: 1;
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uint32_t carrier_en: 1;
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uint32_t carrier_out_lv: 1;
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uint32_t reserved30: 2;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t tx_start: 1;
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uint32_t rx_en: 1;
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uint32_t mem_wr_rst: 1;
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uint32_t mem_rd_rst: 1;
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uint32_t apb_mem_rst: 1;
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uint32_t mem_owner: 1;
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uint32_t tx_conti_mode: 1;
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uint32_t rx_filter_en: 1;
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uint32_t rx_filter_thres: 8;
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uint32_t chk_rx_carrier_en: 1;
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uint32_t ref_always_on: 1;
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uint32_t idle_out_lv: 1;
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uint32_t idle_out_en: 1;
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uint32_t tx_stop: 1;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} conf1;
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} conf_ch[4];
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union {
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struct {
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uint32_t mem_waddr_ex: 9;
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uint32_t reserved9: 1;
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uint32_t mem_raddr_ex: 9;
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uint32_t reserved19: 1;
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uint32_t state: 3;
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uint32_t mem_owner_err: 1;
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uint32_t mem_full: 1;
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uint32_t mem_empty: 1;
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uint32_t apb_mem_wr_err: 1;
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uint32_t apb_mem_rd_err: 1;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} status_ch[4];
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union {
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struct {
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uint32_t waddr: 9;
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uint32_t reserved9: 1;
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uint32_t raddr: 9;
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uint32_t reserved19: 13;
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};
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uint32_t val;
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} apb_mem_addr_ch[4];
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch0_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch1_rx_end: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_tx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_tx_thr_event: 1;
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uint32_t ch3_tx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t ch2_tx_loop: 1;
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uint32_t ch3_tx_loop: 1;
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uint32_t ch0_rx_thr_event: 1;
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uint32_t ch1_rx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch0_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch1_rx_end: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_tx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_tx_thr_event: 1;
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uint32_t ch3_tx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t ch2_tx_loop: 1;
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uint32_t ch3_tx_loop: 1;
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uint32_t ch0_rx_thr_event: 1;
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uint32_t ch1_rx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch0_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch1_rx_end: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_tx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_tx_thr_event: 1;
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uint32_t ch3_tx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t ch2_tx_loop: 1;
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uint32_t ch3_tx_loop: 1;
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uint32_t ch0_rx_thr_event: 1;
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uint32_t ch1_rx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch0_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch1_rx_end: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_tx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_tx_thr_event: 1;
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uint32_t ch3_tx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t ch2_tx_loop: 1;
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uint32_t ch3_tx_loop: 1;
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uint32_t ch0_rx_thr_event: 1;
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uint32_t ch1_rx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t low: 16;
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uint32_t high: 16;
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};
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uint32_t val;
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} carrier_duty_ch[4];
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union {
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struct {
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uint32_t limit: 9;
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uint32_t tx_loop_num: 10;
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uint32_t tx_loop_cnt_en: 1;
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uint32_t loop_count_reset: 1;
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uint32_t rx_lim: 9;
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uint32_t reserved30: 2;
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};
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uint32_t val;
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} tx_lim_ch[4];
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union {
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struct {
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uint32_t fifo_mask: 1;
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uint32_t mem_tx_wrap_en: 1;
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uint32_t mem_clk_force_on: 1;
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uint32_t mem_force_pd: 1;
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uint32_t mem_force_pu: 1;
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uint32_t reserved5: 26;
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uint32_t clk_en: 1;
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};
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uint32_t val;
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} apb_conf;
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union {
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struct {
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uint32_t ch0: 1;
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uint32_t ch1: 1;
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uint32_t ch2: 1;
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uint32_t ch3: 1;
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uint32_t en: 1;
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uint32_t reserved5: 27;
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};
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uint32_t val;
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} tx_sim;
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union {
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struct {
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uint32_t ch0: 1;
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uint32_t ch1: 1;
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uint32_t ch2: 1;
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uint32_t ch3: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} ref_cnt_rst;
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union {
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struct {
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uint32_t carrier_low_thres_ch: 16;
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uint32_t carrier_high_thres_ch:16;
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};
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uint32_t val;
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} ch_rx_carrier_rm[4];
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uint32_t reserved_9c;
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uint32_t reserved_a0;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t date; /* Version Control Register */
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} rmt_dev_t;
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extern rmt_dev_t RMT;
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typedef struct {
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union {
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struct {
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uint32_t duration0 :15;
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uint32_t level0 :1;
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uint32_t duration1 :15;
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uint32_t level1 :1;
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};
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uint32_t val;
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};
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} rmt_item32_t;
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//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
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typedef volatile struct rmt_mem_s {
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struct {
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rmt_item32_t data32[64];
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} chan[4];
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} rmt_mem_t;
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extern rmt_mem_t RMTMEM;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_RMT_STRUCT_H_ */
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