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https://github.com/espressif/esp-idf.git
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106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ESP_CPU_H
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#define _ESP_CPU_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "hal/cpu_hal.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ESP_WATCHPOINT_LOAD 0x40000000
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#define ESP_WATCHPOINT_STORE 0x80000000
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#define ESP_WATCHPOINT_ACCESS 0xC0000000
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typedef uint32_t esp_cpu_ccount_t;
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/** @brief Read current stack pointer address
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*
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*/
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static inline void *esp_cpu_get_sp(void)
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{
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return cpu_hal_get_sp();
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}
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/**
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* @brief Stall CPU using RTC controller
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* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
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*/
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void esp_cpu_stall(int cpu_id);
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/**
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* @brief Un-stall CPU using RTC controller
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* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
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*/
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void esp_cpu_unstall(int cpu_id);
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/**
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* @brief Reset CPU using RTC controller
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* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
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*/
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void esp_cpu_reset(int cpu_id);
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/**
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* @brief Returns true if a JTAG debugger is attached to CPU
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* OCD (on chip debug) port.
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*
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* @note If "Make exception and panic handlers JTAG/OCD aware"
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* is disabled, this function always returns false.
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*/
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bool esp_cpu_in_ocd_debug_mode(void);
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static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
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{
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return cpu_hal_get_cycle_count();
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}
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static inline void esp_cpu_set_ccount(esp_cpu_ccount_t val)
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{
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cpu_hal_set_cycle_count(val);
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}
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/**
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* @brief Set and enable a hardware watchpoint on the current CPU
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*
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* Set and enable a hardware watchpoint on the current CPU, specifying the
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* memory range and trigger operation. Watchpoints will break/panic the CPU when
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* the CPU accesses (according to the trigger type) on a certain memory range.
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*
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* @note Overwrites previously set watchpoint with same watchpoint number.
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* On RISC-V chips, this API uses method0(Exact matching) and method1(NAPOT matching) according to the
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* riscv-debug-spec-0.13 specification for address matching.
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* If the watch region size is 1byte, it uses exact matching (method 0).
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* If the watch region size is larger than 1byte, it uses NAPOT matching (method 1). This mode requires
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* the watching region start address to be aligned to the watching region size.
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*
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* @param no Hardware watchpoint number [0..SOC_CPU_WATCHPOINTS_NUM - 1]
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* @param adr Watchpoint's base address, must be naturally aligned to the size of the region
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* @param size Size of the region to watch. Must be one of 2^n and in the range of [1 ... SOC_CPU_WATCHPOINT_SIZE]
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* @param flags One of ESP_WATCHPOINT_* flags
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* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
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*/
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esp_err_t esp_cpu_set_watchpoint(int no, void *adr, int size, int flags);
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/**
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* @brief Clear a watchpoint
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*
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* @param no Watchpoint to clear
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*
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*/
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void esp_cpu_clear_watchpoint(int no);
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#ifdef __cplusplus
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}
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#endif
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#endif // _ESP_CPU_H
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