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319 lines
12 KiB
C
319 lines
12 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** ECDSA_CONF_REG register
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* ECDSA configure register
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*/
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#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
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/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
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* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
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* Generate Mode. 2: Export Public Key Mode. 3: invalid.
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*/
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#define ECDSA_WORK_MODE 0x00000003U
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#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
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#define ECDSA_WORK_MODE_V 0x00000003U
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#define ECDSA_WORK_MODE_S 0
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/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
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* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
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*/
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#define ECDSA_ECC_CURVE (BIT(2))
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#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
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#define ECDSA_ECC_CURVE_V 0x00000001U
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#define ECDSA_ECC_CURVE_S 2
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/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
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* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
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* written by software.
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*/
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#define ECDSA_SOFTWARE_SET_K (BIT(3))
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#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
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#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
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#define ECDSA_SOFTWARE_SET_K_S 3
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/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
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* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
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* software.
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*/
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#define ECDSA_SOFTWARE_SET_Z (BIT(4))
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#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
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#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
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#define ECDSA_SOFTWARE_SET_Z_S 4
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/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
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* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
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* deterministic derivation algorithm.
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*/
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#define ECDSA_DETERMINISTIC_K (BIT(5))
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#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
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#define ECDSA_DETERMINISTIC_K_V 0x00000001U
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#define ECDSA_DETERMINISTIC_K_S 5
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/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
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* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
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*/
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#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
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#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
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#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
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#define ECDSA_DETERMINISTIC_LOOP_S 6
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/** ECDSA_CLK_REG register
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* ECDSA clock gate register
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*/
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#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
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/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
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* Write 1 to force on register clock gate.
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*/
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#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
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#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
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#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
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#define ECDSA_CLK_GATE_FORCE_ON_S 0
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/** ECDSA_INT_RAW_REG register
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* ECDSA interrupt raw register, valid in level.
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*/
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#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
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/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_RAW (BIT(0))
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#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
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#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_RAW_S 0
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/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
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#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_RAW_S 1
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/** ECDSA_INT_ST_REG register
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* ECDSA interrupt status register.
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*/
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#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
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/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_ST (BIT(0))
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#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
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#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_ST_S 0
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/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_ST (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
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#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_ST_S 1
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/** ECDSA_INT_ENA_REG register
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* ECDSA interrupt enable register.
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*/
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#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
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/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_ENA (BIT(0))
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#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
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#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_ENA_S 0
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/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
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#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_ENA_S 1
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/** ECDSA_INT_CLR_REG register
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* ECDSA interrupt clear register.
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*/
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#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
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/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_CLR (BIT(0))
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#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
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#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_CLR_S 0
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/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
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#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_CLR_S 1
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/** ECDSA_START_REG register
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* ECDSA start register
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*/
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#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
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/** ECDSA_START : WT; bitpos: [0]; default: 0;
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* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
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* after configuration.
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*/
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#define ECDSA_START (BIT(0))
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#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
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#define ECDSA_START_V 0x00000001U
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#define ECDSA_START_S 0
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/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
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* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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#define ECDSA_LOAD_DONE (BIT(1))
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#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
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#define ECDSA_LOAD_DONE_V 0x00000001U
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#define ECDSA_LOAD_DONE_S 1
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/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
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* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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#define ECDSA_GET_DONE (BIT(2))
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#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
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#define ECDSA_GET_DONE_V 0x00000001U
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#define ECDSA_GET_DONE_S 2
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/** ECDSA_STATE_REG register
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* ECDSA status register
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*/
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#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
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/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
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* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
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* state.
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*/
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#define ECDSA_BUSY 0x00000003U
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#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
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#define ECDSA_BUSY_V 0x00000003U
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#define ECDSA_BUSY_S 0
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/** ECDSA_RESULT_REG register
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* ECDSA result register
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*/
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#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
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/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
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* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
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* done.
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*/
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#define ECDSA_OPERATION_RESULT (BIT(0))
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#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
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#define ECDSA_OPERATION_RESULT_V 0x00000001U
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#define ECDSA_OPERATION_RESULT_S 0
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/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
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* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
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* curve order, then actually taken k = k mod n.
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*/
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#define ECDSA_K_VALUE_WARNING (BIT(1))
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#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
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#define ECDSA_K_VALUE_WARNING_V 0x00000001U
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#define ECDSA_K_VALUE_WARNING_S 1
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/** ECDSA_DATE_REG register
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* Version control register
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*/
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#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
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/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
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* ECDSA version control register
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*/
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#define ECDSA_DATE 0x0FFFFFFFU
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#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
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#define ECDSA_DATE_V 0x0FFFFFFFU
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#define ECDSA_DATE_S 0
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/** ECDSA_SHA_MODE_REG register
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* ECDSA control SHA register
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*/
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#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
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/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
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* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
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* Others: invalid.
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*/
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#define ECDSA_SHA_MODE 0x00000007U
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#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
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#define ECDSA_SHA_MODE_V 0x00000007U
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#define ECDSA_SHA_MODE_S 0
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/** ECDSA_SHA_START_REG register
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* ECDSA control SHA register
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*/
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#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
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/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
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* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
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* bit will be self-cleared after configuration.
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*/
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#define ECDSA_SHA_START (BIT(0))
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#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
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#define ECDSA_SHA_START_V 0x00000001U
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#define ECDSA_SHA_START_S 0
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/** ECDSA_SHA_CONTINUE_REG register
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* ECDSA control SHA register
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*/
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#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
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/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
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* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
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* bit will be self-cleared after configuration.
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*/
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#define ECDSA_SHA_CONTINUE (BIT(0))
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#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
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#define ECDSA_SHA_CONTINUE_V 0x00000001U
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#define ECDSA_SHA_CONTINUE_S 0
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/** ECDSA_SHA_BUSY_REG register
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* ECDSA status register
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*/
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#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
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/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
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* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
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* calculation. 0: SHA is idle.
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*/
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#define ECDSA_SHA_BUSY (BIT(0))
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#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
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#define ECDSA_SHA_BUSY_V 0x00000001U
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#define ECDSA_SHA_BUSY_S 0
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/** ECDSA_MESSAGE_MEM register
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* The memory that stores message.
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*/
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#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
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#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
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/** ECDSA_R_MEM register
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* The memory that stores r.
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*/
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#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
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#define ECDSA_R_MEM_SIZE_BYTES 32
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/** ECDSA_S_MEM register
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* The memory that stores s.
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*/
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#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
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#define ECDSA_S_MEM_SIZE_BYTES 32
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/** ECDSA_Z_MEM register
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* The memory that stores software written z.
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*/
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#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
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#define ECDSA_Z_MEM_SIZE_BYTES 32
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/** ECDSA_QAX_MEM register
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* The memory that stores x coordinates of QA or software written k.
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*/
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#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
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#define ECDSA_QAX_MEM_SIZE_BYTES 32
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/** ECDSA_QAY_MEM register
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* The memory that stores y coordinates of QA.
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*/
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#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
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#define ECDSA_QAY_MEM_SIZE_BYTES 32
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#ifdef __cplusplus
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}
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#endif
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