mirror of
https://github.com/espressif/esp-idf.git
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437 lines
15 KiB
C
437 lines
15 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Control and configuration registers */
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/** Type of tx_inst_cfg0 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
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* write this bits to specify the one of 8 instruction
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*/
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uint32_t tx_inst_idx:3;
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/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
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* write this bits to specify the bit position of 257 bit instruction which in units
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* of 32 bits
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*/
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uint32_t tx_inst_pos:4;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} bitscrambler_tx_inst_cfg0_reg_t;
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/** Type of tx_inst_cfg1 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** tx_inst : R/W; bitpos: [31:0]; default: 4;
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* write this bits to update instruction which specified by
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* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
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* BITSCRAMBLER_TX_INST_CFG0_REG
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*/
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uint32_t tx_inst:32;
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};
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uint32_t val;
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} bitscrambler_tx_inst_cfg1_reg_t;
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/** Type of rx_inst_cfg0 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
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* write this bits to specify the one of 8 instruction
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*/
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uint32_t rx_inst_idx:3;
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/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
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* write this bits to specify the bit position of 257 bit instruction which in units
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* of 32 bits
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*/
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uint32_t rx_inst_pos:4;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} bitscrambler_rx_inst_cfg0_reg_t;
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/** Type of rx_inst_cfg1 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** rx_inst : R/W; bitpos: [31:0]; default: 12;
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* write this bits to update instruction which specified by
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* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
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* BITSCRAMBLER_RX_INST_CFG0_REG
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*/
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uint32_t rx_inst:32;
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};
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uint32_t val;
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} bitscrambler_rx_inst_cfg1_reg_t;
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/** Type of tx_lut_cfg0 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
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* write this bits to specify the bytes position of LUT RAM based on
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* reg_bitscrambler_tx_lut_mode
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*/
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uint32_t tx_lut_idx:11;
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/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
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* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
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* bytes
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*/
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uint32_t tx_lut_mode:2;
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uint32_t reserved_13:19;
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};
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uint32_t val;
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} bitscrambler_tx_lut_cfg0_reg_t;
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/** Type of tx_lut_cfg1 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** tx_lut : R/W; bitpos: [31:0]; default: 20;
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* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
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* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
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*/
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uint32_t tx_lut:32;
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};
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uint32_t val;
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} bitscrambler_tx_lut_cfg1_reg_t;
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/** Type of rx_lut_cfg0 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
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* write this bits to specify the bytes position of LUT RAM based on
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* reg_bitscrambler_rx_lut_mode
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*/
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uint32_t rx_lut_idx:11;
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/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
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* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
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* bytes
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*/
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uint32_t rx_lut_mode:2;
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uint32_t reserved_13:19;
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};
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uint32_t val;
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} bitscrambler_rx_lut_cfg0_reg_t;
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/** Type of rx_lut_cfg1 register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** rx_lut : R/W; bitpos: [31:0]; default: 28;
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* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
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* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
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*/
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uint32_t rx_lut:32;
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};
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uint32_t val;
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} bitscrambler_rx_lut_cfg1_reg_t;
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/** Group: Configuration registers */
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/** Type of tx_tailing_bits register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
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* write this bits to specify the extra data bit length after getting EOF
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*/
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uint32_t tx_tailing_bits:16;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} bitscrambler_tx_tailing_bits_reg_t;
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/** Type of rx_tailing_bits register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
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* write this bits to specify the extra data bit length after getting EOF
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*/
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uint32_t rx_tailing_bits:16;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} bitscrambler_rx_tailing_bits_reg_t;
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/** Type of tx_ctrl register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** tx_ena : R/W; bitpos: [0]; default: 0;
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* write this bit to enable the bitscrambler tx
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*/
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uint32_t tx_ena:1;
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/** tx_pause : R/W; bitpos: [1]; default: 0;
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* write this bit to pause the bitscrambler tx core
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*/
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uint32_t tx_pause:1;
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/** tx_halt : R/W; bitpos: [2]; default: 1;
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* write this bit to halt the bitscrambler tx core
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*/
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uint32_t tx_halt:1;
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/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
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* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
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* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
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* counter by write peripheral buffer
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*/
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uint32_t tx_eof_mode:1;
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/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
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* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
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* core, 0: use the little than operator to get the condition, 1: use not equal
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* operator to get the condition
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*/
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uint32_t tx_cond_mode:1;
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/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
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* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
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* by reset, 1: fetch by instrutions
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*/
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uint32_t tx_fetch_mode:1;
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/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
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* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
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* wait write data back done, , 1: ignore write data back
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*/
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uint32_t tx_halt_mode:1;
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/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
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* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
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* wait read data, 1: ignore read data
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*/
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uint32_t tx_rd_dummy:1;
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/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
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* write this bit to reset the bitscrambler tx fifo
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*/
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uint32_t tx_fifo_rst:1;
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uint32_t reserved_9:23;
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};
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uint32_t val;
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} bitscrambler_tx_ctrl_reg_t;
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/** Type of rx_ctrl register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** rx_ena : R/W; bitpos: [0]; default: 0;
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* write this bit to enable the bitscrambler rx
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*/
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uint32_t rx_ena:1;
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/** rx_pause : R/W; bitpos: [1]; default: 0;
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* write this bit to pause the bitscrambler rx core
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*/
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uint32_t rx_pause:1;
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/** rx_halt : R/W; bitpos: [2]; default: 1;
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* write this bit to halt the bitscrambler rx core
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*/
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uint32_t rx_halt:1;
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/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
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* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
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* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
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* buffer, 0 counter by write dma fifo
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*/
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uint32_t rx_eof_mode:1;
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/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
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* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
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* core, 0: use the little than operator to get the condition, 1: use not equal
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* operator to get the condition
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*/
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uint32_t rx_cond_mode:1;
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/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
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* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
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* by reset, 1: fetch by instrutions
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*/
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uint32_t rx_fetch_mode:1;
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/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
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* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
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* wait write data back done, , 1: ignore write data back
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*/
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uint32_t rx_halt_mode:1;
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/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
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* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
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* wait read data, 1: ignore read data
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*/
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uint32_t rx_rd_dummy:1;
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/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
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* write this bit to reset the bitscrambler rx fifo
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*/
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uint32_t rx_fifo_rst:1;
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uint32_t reserved_9:23;
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};
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uint32_t val;
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} bitscrambler_rx_ctrl_reg_t;
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/** Type of sys register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** loop_mode : R/W; bitpos: [0]; default: 0;
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* write this bit to set the bitscrambler tx loop back to DMA rx
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*/
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uint32_t loop_mode:1;
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uint32_t reserved_1:30;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* Reserved
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*/
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uint32_t clk_en:1;
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};
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uint32_t val;
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} bitscrambler_sys_reg_t;
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/** Group: Status registers */
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/** Type of tx_state register
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* Status registers
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*/
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typedef union {
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struct {
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/** tx_in_idle : RO; bitpos: [0]; default: 1;
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* represents the bitscrambler tx core in halt mode
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*/
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uint32_t tx_in_idle:1;
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/** tx_in_run : RO; bitpos: [1]; default: 0;
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* represents the bitscrambler tx core in run mode
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*/
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uint32_t tx_in_run:1;
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/** tx_in_wait : RO; bitpos: [2]; default: 0;
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* represents the bitscrambler tx core in wait mode to wait write back done
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*/
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uint32_t tx_in_wait:1;
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/** tx_in_pause : RO; bitpos: [3]; default: 0;
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* represents the bitscrambler tx core in pause mode
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*/
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uint32_t tx_in_pause:1;
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/** tx_fifo_empty : RO; bitpos: [4]; default: 0;
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* represents the bitscrambler tx fifo in empty state
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*/
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uint32_t tx_fifo_empty:1;
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uint32_t reserved_5:11;
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/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
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* represents the bytes numbers of bitscrambler tx core when get EOF
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*/
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uint32_t tx_eof_get_cnt:14;
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/** tx_eof_overload : RO; bitpos: [30]; default: 0;
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* represents the some EOFs will be lost for bitscrambler tx core
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*/
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uint32_t tx_eof_overload:1;
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/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
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* write this bit to clear reg_bitscrambler_tx_eof_overload and
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* reg_bitscrambler_tx_eof_get_cnt registers
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*/
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uint32_t tx_eof_trace_clr:1;
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};
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uint32_t val;
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} bitscrambler_tx_state_reg_t;
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/** Type of rx_state register
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* Status registers
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*/
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typedef union {
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struct {
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/** rx_in_idle : RO; bitpos: [0]; default: 1;
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* represents the bitscrambler rx core in halt mode
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*/
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uint32_t rx_in_idle:1;
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/** rx_in_run : RO; bitpos: [1]; default: 0;
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* represents the bitscrambler rx core in run mode
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*/
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uint32_t rx_in_run:1;
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/** rx_in_wait : RO; bitpos: [2]; default: 0;
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* represents the bitscrambler rx core in wait mode to wait write back done
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*/
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uint32_t rx_in_wait:1;
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/** rx_in_pause : RO; bitpos: [3]; default: 0;
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* represents the bitscrambler rx core in pause mode
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*/
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uint32_t rx_in_pause:1;
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/** rx_fifo_full : RO; bitpos: [4]; default: 0;
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* represents the bitscrambler rx fifo in full state
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*/
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uint32_t rx_fifo_full:1;
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uint32_t reserved_5:11;
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/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
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* represents the bytes numbers of bitscrambler rx core when get EOF
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*/
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uint32_t rx_eof_get_cnt:14;
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/** rx_eof_overload : RO; bitpos: [30]; default: 0;
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* represents the some EOFs will be lost for bitscrambler rx core
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*/
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uint32_t rx_eof_overload:1;
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/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
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* write this bit to clear reg_bitscrambler_rx_eof_overload and
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* reg_bitscrambler_rx_eof_get_cnt registers
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*/
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uint32_t rx_eof_trace_clr:1;
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};
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uint32_t val;
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} bitscrambler_rx_state_reg_t;
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/** Group: Version register */
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/** Type of version register
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* Control and configuration registers
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*/
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typedef union {
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struct {
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/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
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* Reserved
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*/
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uint32_t bitscrambler_ver:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} bitscrambler_version_reg_t;
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typedef struct {
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volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
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volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
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volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
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volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
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volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
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volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
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volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
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volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
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volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
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volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
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volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
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volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
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volatile bitscrambler_tx_state_reg_t tx_state;
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volatile bitscrambler_rx_state_reg_t rx_state;
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uint32_t reserved_038[48];
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volatile bitscrambler_sys_reg_t sys;
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volatile bitscrambler_version_reg_t version;
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} bitscrambler_dev_t;
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#ifndef __cplusplus
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_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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