esp-idf/components/soc
Mahavir Jain 316674a096 Merge branch 'feature/hmac_downstream_jtag_v4.3' into 'release/v4.3'
hmac: Added Downstream JTAG enable mode for esp32c3 (v4.3)

See merge request espressif/esp-idf!15203
2021-09-16 04:20:14 +00:00
..
esp32 component/bt: add local irk to controller 2021-08-06 18:19:25 +08:00
esp32c3 hmac: Added Downstream JTAG enable mode for esp32c3 2021-09-14 17:05:01 +05:30
esp32s2 Merge branch 'feature/support_bss_in_psram_for_esp32s2_v4.3' into 'release/v4.3' 2021-09-15 08:09:42 +00:00
esp32s3 idf_size.py: fixed diram counted twice issue, and improve display 2021-09-01 16:36:47 +02:00
include/soc espcoredump: Fix bugs related to (fake) stacks 2021-05-28 01:58:09 +00:00
CMakeLists.txt soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
component.mk Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
linker.lf soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
lldesc.c soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
memory_layout_utils.c esp_rom: Add initial ESP32-C3 support 2020-11-30 11:12:56 +11:00
README.md soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
soc_include_legacy_warn.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware