esp-idf/components/riscv
Martin Vychodil 69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00
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include Security: ESP32C3 memory protection feature (IRAM0/DRAM0) 2021-01-27 08:44:03 +01:00
CMakeLists.txt interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
expression_with_stack_riscv_asm.S esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
expression_with_stack_riscv.c esp_shared_stack: enable shared stack function for riscv and reenable the unit test 2021-01-05 15:39:46 +08:00
instruction_decode.c interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
interrupt.c interrupt: removed descriptor table from esp32c3 interrupt hal. 2021-01-05 15:39:46 +08:00
linker.lf riscv: Place stdatomic file in iram 2020-12-24 14:18:01 +11:00
stdatomic.c riscv: Add new arch-level component 2020-11-12 09:33:18 +11:00
vectors.S Security: ESP32C3 memory protection feature (IRAM0/DRAM0) 2021-01-27 08:44:03 +01:00