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https://github.com/espressif/esp-idf.git
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116 lines
4.0 KiB
C
116 lines
4.0 KiB
C
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_attr.h"
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#include "esp_wifi.h"
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#include "esp_log.h"
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#include "esp32s2/rom/cache.h"
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#include "esp32s2/rom/uart.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_reg.h"
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#include "soc/timer_group_struct.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/rtc_wdt.h"
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#include "soc/syscon_reg.h"
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#include "freertos/xtensa_api.h"
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void IRAM_ATTR esp_restart_noos(void)
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{
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// Disable interrupts
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xt_ints_off(0xFFFFFFFF);
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// Enable RTC watchdog for 1 second
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rtc_wdt_protect_off();
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rtc_wdt_disable();
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rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_RTC);
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rtc_wdt_set_stage(RTC_WDT_STAGE1, RTC_WDT_STAGE_ACTION_RESET_SYSTEM);
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rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_200ns);
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rtc_wdt_set_length_of_reset_signal(RTC_WDT_CPU_RESET_SIG, RTC_WDT_LENGTH_200ns);
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rtc_wdt_set_time(RTC_WDT_STAGE0, 1000);
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rtc_wdt_flashboot_mode_enable();
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// Reset and stall the other CPU.
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// CPU must be reset before stalling, in case it was running a s32c1i
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// instruction. This would cause memory pool to be locked by arbiter
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// to the stalled CPU, preventing current CPU from accessing this pool.
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const uint32_t core_id = xPortGetCoreID();
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// Disable TG0/TG1 watchdogs
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TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_config0.en = 0;
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TIMERG0.wdt_wprotect = 0;
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TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG1.wdt_config0.en = 0;
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TIMERG1.wdt_wprotect = 0;
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// Flush any data left in UART FIFOs
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uart_tx_wait_idle(0);
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uart_tx_wait_idle(1);
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// Disable cache
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Cache_Disable_ICache();
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Cache_Disable_DCache();
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// 2nd stage bootloader reconfigures SPI flash signals.
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// Reset them to the defaults expected by ROM.
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
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DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
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DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
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DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
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DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
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DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
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DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
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// Reset timer/spi/uart
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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rtc_clk_cpu_freq_set_xtal();
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// Reset CPUs
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if (core_id == 0) {
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esp_cpu_reset(0);
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}
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while (true) {
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;
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}
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}
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void esp_chip_info(esp_chip_info_t *out_info)
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{
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memset(out_info, 0, sizeof(*out_info));
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out_info->model = CHIP_ESP32S2;
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out_info->cores = 1;
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out_info->features = CHIP_FEATURE_WIFI_BGN;
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}
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