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https://github.com/espressif/esp-idf.git
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e10202a608
* Support intel 8080 LCD panel IO on ESP32-S3 * Support RGB LCD panel on ESP32-S3 * Support SPI && I2C LCD panel IO on all esp chips
78 lines
3.6 KiB
C
78 lines
3.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "esp_err.h"
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#include "esp_lcd_types.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_LCD_RGB_SUPPORTED
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/**
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* @brief LCD RGB timing structure
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*/
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typedef struct {
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unsigned int pclk_hz; /*!< Frequency of pixel clock */
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unsigned int h_res; /*!< Horizontal resolution, i.e. the number of pixels in a line */
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unsigned int v_res; /*!< Vertical resolution, i.e. the number of lines in the frame */
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unsigned int hsync_pulse_width; /*!< Horizontal sync width, unit: PCLK period */
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unsigned int hsync_back_porch; /*!< Horizontal back porch, number of PCLK between hsync and start of line active data */
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unsigned int hsync_front_porch; /*!< Horizontal front porch, number of PCLK between the end of active data and the next hsync */
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unsigned int vsync_pulse_width; /*!< Vertical sync width, unit: number of lines */
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unsigned int vsync_back_porch; /*!< Vertical back porch, number of invalid lines between vsync and start of frame */
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unsigned int vsync_front_porch; /*!< Vertical front porch, number of invalid lines between then end of frame and the next vsync */
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struct {
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unsigned int hsync_idle_low: 1; /*!< The hsync signal is low in IDLE state */
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unsigned int vsync_idle_low: 1; /*!< The vsync signal is low in IDLE state */
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unsigned int de_idle_high: 1; /*!< The de signal is high in IDLE state */
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unsigned int pclk_active_neg: 1; /*!< The display will write data lines when there's a falling edge on PCLK */
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unsigned int pclk_idle_low: 1; /*!< The PCLK stays at low level in IDLE phase */
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} flags;
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} esp_lcd_rgb_timing_t;
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/**
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* @brief LCD RGB panel configuration structure
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*/
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typedef struct {
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esp_lcd_rgb_timing_t timings; /*!< RGB timing parameters */
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size_t data_width; /*!< Number of data lines */
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int hsync_gpio_num; /*!< GPIO used for HSYNC signal */
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int vsync_gpio_num; /*!< GPIO used for VSYNC signal */
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int de_gpio_num; /*!< GPIO used for DE signal, set to -1 if it's not used */
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int pclk_gpio_num; /*!< GPIO used for PCLK signal */
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int data_gpio_nums[SOC_LCD_RGB_DATA_WIDTH]; /*!< GPIOs used for data lines */
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int disp_gpio_num; /*!< GPIO used for display control signal, set to -1 if it's not used */
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bool (*on_frame_trans_done)(esp_lcd_panel_handle_t panel, void *user_data); /*!< Callback, invoked when one frame buffer has transferred done */
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void *user_data; /*!< User data which would be passed to on_frame_trans_done's user_data */
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struct {
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unsigned int disp_active_low: 1; /*!< If this flag is enabled, a low level of display control signal can turn the screen on; vice versa */
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unsigned int relax_on_idle: 1; /*!< If this flag is enabled, the host won't refresh the LCD if nothing changed in host's frame buffer (this is usefull for LCD with built-in GRAM) */
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} flags;
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} esp_lcd_rgb_panel_config_t;
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/**
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* @brief Create RGB LCD panel
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*
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* @param rgb_panel_config RGB panel configuration
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* @param ret_panel Returned LCD panel handle
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* @return
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* - ESP_ERR_INVALID_ARG if parameter is invalid
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* - ESP_ERR_NO_MEM if out of memory
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* - ESP_ERR_NOT_FOUND if no free RGB panel is available
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* - ESP_OK on success
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*/
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esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_config, esp_lcd_panel_handle_t *ret_panel);
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#endif // SOC_LCD_RGB_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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