mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
475 lines
15 KiB
C
475 lines
15 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdbool.h>
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#include <stddef.h>
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#include "hal/misc.h"
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#include "soc/rmt_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RMT_LL_HW_BASE (&RMT)
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#define RMT_LL_MEM_BASE (&RMTMEM)
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// Note: TX and RX channel number are all index from zero in the LL driver
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// i.e. tx_channel belongs to [0,3], and rx_channel belongs to [0,3]
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static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
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{
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dev->apb_conf.clk_en = enable; // register clock gating
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dev->apb_conf.mem_clk_force_on = enable; // memory clock gating
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}
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static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
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{
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dev->apb_conf.mem_force_pu = !enable;
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dev->apb_conf.mem_force_pd = enable;
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}
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static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev)
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{
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// the RTC domain can also power down RMT memory
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// so it's probably not enough to detect whether it's powered down or not
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// mem_force_pd has higher priority than mem_force_pu
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return (dev->apb_conf.mem_force_pd) || !(dev->apb_conf.mem_force_pu);
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}
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static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
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{
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dev->apb_conf.fifo_mask = enable;
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}
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static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b)
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{
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dev->conf_ch[channel].conf1.ref_always_on = src;
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}
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static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->conf_ch[channel].conf1.ref_always_on;
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}
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static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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dev->ref_cnt_rst.val |= (1 << channel);
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}
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static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask)
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{
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dev->ref_cnt_rst.val |= channel_mask;
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}
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static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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dev->ref_cnt_rst.val |= (1 << channel);
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}
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static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->conf_ch[channel].conf1.mem_rd_rst = 1;
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dev->conf_ch[channel].conf1.mem_rd_rst = 0;
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}
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static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->conf_ch[channel].conf1.mem_wr_rst = 1;
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dev->conf_ch[channel].conf1.mem_wr_rst = 0;
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}
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static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
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{
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dev->conf_ch[channel].conf1.tx_start = 1;
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}
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static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
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{
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dev->conf_ch[channel].conf1.tx_stop = 1;
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}
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static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf1.rx_en = enable;
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}
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static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
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{
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dev->conf_ch[channel].conf0.mem_size = block_num;
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}
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static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
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{
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dev->conf_ch[channel].conf0.mem_size = block_num;
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}
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static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->conf_ch[channel].conf0.mem_size;
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}
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static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->conf_ch[channel].conf0.mem_size;
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}
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static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
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}
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static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
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}
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static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
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return div == 0 ? 256 : div;
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}
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static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
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return div == 0 ? 256 : div;
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}
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static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->apb_conf.mem_tx_wrap_en = enable;
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}
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static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);
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}
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static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
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{
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return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);
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}
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static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
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{
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dev->conf_ch[channel].conf1.mem_owner = owner;
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}
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static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->conf_ch[channel].conf1.mem_owner;
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}
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static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf1.tx_conti_mode = enable;
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}
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static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->conf_ch[channel].conf1.tx_conti_mode;
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}
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static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
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{
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dev->tx_lim_ch[channel].tx_loop_num = count;
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}
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static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_lim_ch[channel].loop_count_reset = 1;
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dev->tx_lim_ch[channel].loop_count_reset = 0;
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}
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static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->tx_lim_ch[channel].tx_loop_cnt_en = enable;
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}
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static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable)
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{
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dev->tx_sim.en = enable;
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}
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static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_sim.val |= 1 << channel;
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}
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static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_sim.val &= ~(1 << channel);
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}
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static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf1.rx_filter_en = enable;
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}
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static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);
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}
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static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf1.idle_out_en = enable;
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}
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static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->conf_ch[channel].conf1.idle_out_en;
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}
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static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
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{
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dev->conf_ch[channel].conf1.idle_out_lv = level;
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}
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static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->conf_ch[channel].conf1.idle_out_lv;
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}
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static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->status_ch[channel].val;
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}
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static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->status_ch[channel].val;
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}
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static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
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{
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dev->tx_lim_ch[channel].limit = limit;
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}
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static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
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{
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dev->tx_lim_ch[channel].rx_lim = limit;
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}
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static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->tx_lim_ch[channel].rx_lim;
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}
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static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->int_ena.val |= mask;
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} else {
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dev->int_ena.val &= ~mask;
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}
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}
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static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->int_ena.val &= ~(1 << (channel * 3));
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dev->int_ena.val |= (enable << (channel * 3));
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}
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static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->int_ena.val &= ~(1 << (channel * 3 + 1));
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dev->int_ena.val |= (enable << (channel * 3 + 1));
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}
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static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->int_ena.val &= ~(1 << (channel * 3 + 2));
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dev->int_ena.val |= (enable << (channel * 3 + 2));
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}
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static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->int_ena.val &= ~(1 << (channel * 3 + 2));
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dev->int_ena.val |= (enable << (channel * 3 + 2));
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}
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static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->int_ena.val &= ~(1 << (channel + 12));
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dev->int_ena.val |= (enable << (channel + 12));
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}
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static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->int_ena.val &= ~(1 << (channel + 16));
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dev->int_ena.val |= (enable << (channel + 16));
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}
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static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->int_ena.val &= ~(1 << (channel + 20));
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dev->int_ena.val |= (enable << (channel + 20));
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}
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static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
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{
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dev->int_clr.val = (1 << (channel * 3));
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}
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static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
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{
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dev->int_clr.val = (1 << (channel * 3 + 1));
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}
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static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel)
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{
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dev->int_clr.val = (1 << (channel * 3 + 2));
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}
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static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel)
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{
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dev->int_clr.val = (1 << (channel * 3 + 2));
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}
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static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
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{
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dev->int_clr.val = (1 << (channel + 12));
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}
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static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel)
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{
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dev->int_clr.val = (1 << (channel + 16));
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}
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static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
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{
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dev->int_clr.val = (1 << (channel + 20));
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}
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static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
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{
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uint32_t status = dev->int_st.val;
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return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6);
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}
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static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
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{
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uint32_t status = dev->int_st.val;
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return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7);
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}
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static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev)
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{
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uint32_t status = dev->int_st.val;
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return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8);
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}
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static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev)
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{
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uint32_t status = dev->int_st.val;
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return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8);
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}
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static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
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{
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uint32_t status = dev->int_st.val;
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return (status & 0xF000) >> 12;
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}
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static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
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{
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uint32_t status = dev->int_st.val;
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return (status & 0xF0000) >> 16;
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}
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static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
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{
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uint32_t status = dev->int_st.val;
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return (status & 0xF00000) >> 20;
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}
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static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
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{
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// In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
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// We take care of the "read-modify-write" procedure by ourselves.
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typeof(dev->carrier_duty_ch[0]) reg;
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reg.high = high_ticks;
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reg.low = low_ticks;
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dev->carrier_duty_ch[channel].val = reg.val;
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}
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static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
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{
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typeof(dev->ch_rx_carrier_rm[0]) reg;
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reg.carrier_high_thres_ch = high_ticks;
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reg.carrier_low_thres_ch = low_ticks;
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dev->ch_rx_carrier_rm[channel].val = reg.val;
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}
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static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
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{
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*high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], high);
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*low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], low);
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}
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static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
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{
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*high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_high_thres_ch);
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*low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_low_thres_ch);
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}
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static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
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|
{
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|
dev->conf_ch[channel].conf0.carrier_en = enable;
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|
}
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|
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static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable)
|
|
{
|
|
dev->conf_ch[channel].conf0.carrier_en = enable;
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|
}
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|
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static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
|
|
{
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|
dev->conf_ch[channel].conf0.carrier_out_lv = level;
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|
}
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|
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static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
|
|
{
|
|
dev->conf_ch[channel].conf0.carrier_out_lv = level;
|
|
}
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|
|
|
// set true, enable carrier in all RMT state (idle, reading, sending)
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|
// set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent)
|
|
static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
|
|
{
|
|
dev->conf_ch[channel].conf0.carrier_eff_en = !enable;
|
|
}
|
|
|
|
//Writes items to the specified TX channel memory with the given offset and length.
|
|
//the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL)
|
|
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off)
|
|
{
|
|
volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off];
|
|
uint32_t *from = (uint32_t *)data;
|
|
while (length_in_words--) {
|
|
*to++ = *from++;
|
|
}
|
|
}
|
|
|
|
static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
|
|
{
|
|
dev->conf_ch[channel].conf1.chk_rx_carrier_en = enable;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|