gaoxu 7a2bad690b SPI:fix spi slave example sender ccount issue ...

On riscv core, core cycle counter counts the clock cycles only when core is active (not sleeping).
In spi_slave/sender example, it uses ccount (core cycle counter) to do a simple debounce.
Therefore, when using spi_slave/sender and spi_slave/receiver, program will be stuck.
This commit fix this issue by using esp_timer


(cherry picked from commit afe3bfe19ff1d753dd280bd12ba9c90326cd6ce7)

2022-07-05 11:45:47 +08:00

..

app_main.c

SPI:fix spi slave example sender ccount issue

2022-07-05 11:45:47 +08:00

CMakeLists.txt

Whitespace: Automated whitespace fixes (large commit)

2020-11-11 07:36:35 +00:00

component.mk

Whitespace: Automated whitespace fixes (large commit)

2020-11-11 07:36:35 +00:00