mirror of
https://github.com/espressif/esp-idf.git
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444 lines
12 KiB
C
444 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The ll is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_bit_defs.h"
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#include "hal/assert.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/sdmmc_struct.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "soc/lp_clkrst_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SDMMC_LL_GET_HW(id) (((id) == 0) ? (&SDMMC) : NULL)
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/**
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* SDMMC capabilities
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*/
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#define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) ((SLOT_ID == 0) ? 0 : 1)
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#define SDMMC_LL_IOMUX_FUNC 0
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typedef enum {
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SDMMC_LL_DELAY_PHASE_0,
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SDMMC_LL_DELAY_PHASE_1,
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SDMMC_LL_DELAY_PHASE_2,
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SDMMC_LL_DELAY_PHASE_3,
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} sdmmc_ll_delay_phase_t;
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/**
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* @brief Enable the bus clock for SDMMC module
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*
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* @param hw hardware instance address
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
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{
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HP_SYS_CLKRST.soc_clk_ctrl1.reg_sdmmc_sys_clk_en = en;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the SDMMC module
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw)
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{
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LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 1;
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LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_reset_register(__VA_ARGS__)
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/**
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* @brief Select SDMMC clock source
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*
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* @param hw hardware instance address
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* @param clk_src clock source, see valid sources in type `soc_periph_psram_clk_src_t`
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*/
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static inline void sdmmc_ll_select_clk_source(sdmmc_dev_t *hw, soc_periph_sdmmc_clk_src_t clk_src)
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{
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uint32_t clk_val = 0;
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switch (clk_src) {
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case SDMMC_CLK_SRC_PLL160M:
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clk_val = 0;
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break;
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// case SDMMC_CLK_SRC_PLL200M: // TODO: IDF-8886
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// clk_val = 1;
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// break;
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default:
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HAL_ASSERT(false);
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break;
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}
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HP_SYS_CLKRST.peri_clk_ctrl01.reg_sdio_ls_clk_src_sel = clk_val;
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HP_SYS_CLKRST.peri_clk_ctrl01.reg_sdio_ls_clk_en = true;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_select_clk_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_select_clk_source(__VA_ARGS__)
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/**
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* @brief Set SDMMC clock div
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*
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* @param hw hardware instance address
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* @param div divider value
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*/
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static inline void sdmmc_ll_set_clock_div(sdmmc_dev_t *hw, uint32_t div)
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{
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_h = div / 2 - 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_n = div - 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l = div - 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_set_clock_div(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_set_clock_div(__VA_ARGS__)
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/**
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* @brief Deinit clock
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_deinit_clk(sdmmc_dev_t *hw)
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{
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hw->clk_edge_sel.val = 0;
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}
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/**
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* @brief Get SDMMC clock div
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*
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* @param hw hardware instance address
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*
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* @return Divider value
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*/
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static inline uint32_t sdmmc_ll_get_clock_div(sdmmc_dev_t *hw)
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{
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return HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l + 1;
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}
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/**
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* @brief Initialise the din, dout, self delay phase
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
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{
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_drv_clk_en = 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_en = 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_slf_clk_en = 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_drv_clk_edge_sel = 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_slf_clk_edge_sel = 0;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 1;
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_init_phase_delay(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_init_phase_delay(__VA_ARGS__)
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/**
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* @brief Set SDMMC din delay
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*
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* @param hw hardware instance address
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* @param phase delay phase
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*/
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static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase)
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{
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switch (phase) {
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case SDMMC_LL_DELAY_PHASE_1:
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x1;
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break;
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case SDMMC_LL_DELAY_PHASE_2:
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x2;
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break;
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case SDMMC_LL_DELAY_PHASE_3:
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x3;
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break;
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default:
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HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x0;
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break;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_set_din_delay(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_set_din_delay(__VA_ARGS__)
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/**
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* @brief Enable card clock
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_card_clock(sdmmc_dev_t *hw, uint32_t slot, bool en)
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{
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if (en) {
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hw->clkena.cclk_enable |= BIT(slot);
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} else {
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hw->clkena.cclk_enable &= ~BIT(slot);
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}
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}
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/**
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* @brief Set card clock div
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param card_div divider value
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*/
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static inline void sdmmc_ll_set_card_clock_div(sdmmc_dev_t *hw, uint32_t slot, uint32_t card_div)
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{
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if (slot == 0) {
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hw->clksrc.card0 = 0;
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hw->clkdiv.clk_divider0 = card_div;
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} else if (slot == 1) {
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hw->clksrc.card1 = 1;
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hw->clkdiv.clk_divider1 = card_div;
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} else {
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HAL_ASSERT(false);
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}
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}
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/**
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* @brief Get card clock div
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*
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* @param hw hardware instance address
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* @param slot slot
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*
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* @return Divider value
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*/
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static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slot)
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{
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uint32_t card_div = 0;
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if (slot == 0) {
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HAL_ASSERT(hw->clksrc.card0 == 0);
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card_div = hw->clkdiv.clk_divider0;
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} else if (slot == 1) {
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HAL_ASSERT(hw->clksrc.card1 == 1);
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card_div = hw->clkdiv.clk_divider1;
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} else {
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HAL_ASSERT(false);
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}
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return card_div;
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}
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/**
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* @brief Disable clock when the card is in IDLE state
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_card_clock_low_power(sdmmc_dev_t *hw, uint32_t slot, bool en)
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{
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if (en) {
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hw->clkena.lp_enable |= BIT(slot);
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} else {
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hw->clkena.lp_enable &= ~BIT(slot);
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}
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}
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/**
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* @brief Set card data read timeout cycles
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*
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* @param hw hardware instance address
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* @param timeout_cycles timeout cycles
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*/
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static inline void sdmmc_ll_set_data_timeout(sdmmc_dev_t *hw, uint32_t timeout_cycles)
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{
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if (timeout_cycles > 0xffffff) {
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timeout_cycles = 0xffffff;
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}
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hw->tmout.data_timeout = timeout_cycles;
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}
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/**
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* @brief Set response timeout cycles (in card output clocks)
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*
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* @param hw hardware instance address
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* @param timeout_cycles timeout cycles
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*/
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static inline void sdmmc_ll_set_response_timeout(sdmmc_dev_t *hw, uint32_t timeout_cycles)
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{
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hw->tmout.response_timeout = timeout_cycles;
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}
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/**
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* @brief Check if card is detected
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*
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* @param hw hardware instance address
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* @param slot slot
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*
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* @return True for detected
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*/
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static inline bool sdmmc_ll_is_card_detected(sdmmc_dev_t *hw, uint32_t slot)
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{
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return ((hw->cdetect.card_detect_n & BIT(slot)) == 0);
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}
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/**
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* @brief Check if card is write protected
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*
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* @param hw hardware instance address
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* @param slot slot
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*
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* @return True for write protected
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*/
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static inline bool sdmmc_ll_is_card_write_protected(sdmmc_dev_t *hw, uint32_t slot)
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{
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bool is_protected = hw->wrtprt.write_protect & BIT(slot);
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return is_protected;
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}
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/**
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* @brief Enable DDR mode
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_ddr_mode(sdmmc_dev_t *hw, uint32_t slot, bool en)
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{
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if (en) {
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hw->uhs.ddr |= BIT(slot);
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hw->emmcddr.halfstartbit_reg |= BIT(slot);
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} else {
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hw->uhs.ddr &= ~BIT(slot);
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hw->emmcddr.halfstartbit_reg &= ~BIT(slot);
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}
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}
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/**
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* @brief Set data transfer length
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*
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* @param hw hardware instance address
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* @param len length
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*/
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static inline void sdmmc_ll_set_data_transfer_len(sdmmc_dev_t *hw, uint32_t len)
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{
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hw->bytcnt.byte_count = len;
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}
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/**
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* @brief Set block size
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*
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* @param hw hardware instance address
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* @param block_size block size
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*/
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static inline void sdmmc_ll_set_block_size(sdmmc_dev_t *hw, uint32_t block_size)
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{
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hw->blksiz.block_size = block_size;
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}
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/**
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* @brief Set descriptor addr
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*
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* @param hw hardware instance address
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* @param block_size block size
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*/
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static inline void sdmmc_ll_set_desc_addr(sdmmc_dev_t *hw, uint32_t desc_addr)
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{
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hw->dbaddr.dbaddr_reg = desc_addr;
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}
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/**
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* @brief Enable DMA
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_dma(sdmmc_dev_t *hw, bool en)
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{
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hw->ctrl.dma_enable = en;
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hw->ctrl.use_internal_dma = en;
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hw->bmod.enable = en;
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hw->bmod.fb = en;
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}
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/**
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* @brief Poll demand
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_poll_demand(sdmmc_dev_t *hw)
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{
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hw->pldmnd.pldmnd_pd = 1;
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}
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/**
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* @brief Get interrupt status
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*
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* @param hw hardware instance address
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*/
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static inline uint32_t sdmmc_ll_get_intr_status(sdmmc_dev_t *hw)
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{
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return hw->mintsts.val;
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}
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/**
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* @brief Enable interrupt
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*
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* @param hw hardware instance address
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* @param mask interrupt mask
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_interrupt(sdmmc_dev_t *hw, uint32_t mask, bool en)
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{
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if (en) {
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hw->intmask.val |= mask;
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} else {
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hw->intmask.val &= ~mask;
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}
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}
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/**
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* @brief Clear interrupt
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*
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* @param hw hardware instance address
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* @param mask interrupt mask
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*/
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static inline void sdmmc_ll_clear_interrupt(sdmmc_dev_t *hw, uint32_t mask)
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{
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hw->rintsts.val = mask;
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}
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#ifdef __cplusplus
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}
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#endif
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