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https://github.com/espressif/esp-idf.git
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173 lines
7.5 KiB
C
173 lines
7.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "esp_flash_partitions.h"
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "mspi_timing_tuning_configs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPI_TIMING_CONFIG_NUM_DEFAULT 20 //This should be larger than the max available timing config num
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#define SPI_TIMING_TEST_DATA_LEN 64
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#define SPI_TIMING_PSRAM_TEST_DATA_ADDR 0
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#define SPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET
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//-------------------------------------------FLASH Operation Mode and Corresponding Timing Tuning Parameter Table --------------------------------------//
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#define SPI_TIMING_FLASH_DTR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR || CONFIG_ESPTOOLPY_FLASHMODE_OIO_DTR)
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#define SPI_TIMING_FLASH_STR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR || CONFIG_ESPTOOLPY_FLASHMODE_OIO_STR || CONFIG_ESPTOOLPY_FLASHMODE_OOUT_STR)
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/* Determine A feasible core clock below: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ*/
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//OCTAL FLASH
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#if CONFIG_ESPTOOLPY_OCT_FLASH
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// OCT FLASH 40M DTR
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#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_40M
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_Static_assert(!CONFIG_ESPTOOLPY_FLASHFREQ_40M, "Octal FLASH 40MHz DDR is not supported. TODO: IDF-1630");
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160
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#endif
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//OCT FLASH 80M DTR
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#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160
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#endif
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//OCT FLASH 120M DTR
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#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
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#endif
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//OCT FLASH 80M STR
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#if SPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160
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#endif
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//OCT FLASH 120M STR
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#if SPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120
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#endif
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#endif //#if CONFIG_ESPTOOLPY_OCT_FLASH
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/* QUAD FLASH Operation Mode should be added here if needed */
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//---------------------------------------PSRAM Operation Mode and Corresponding Timing Tuning Parameter Table--------------------------------------//
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#define SPI_TIMING_PSRAM_DTR_MODE 1 //Currently we only support DTR Octal PSRAM
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#define SPI_TIMING_PSRAM_STR_MODE 0
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//OCTAL PSRAM
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#if CONFIG_SPIRAM_MODE_OCT
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//OCT 40M PSRAM
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#if SPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_40M
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#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 80
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#endif
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//OCT 80M PSRAM
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#if SPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_80M
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#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160
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#endif
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#endif //#if CONFIG_SPIRAM_MODE_OCT
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/* QUAD PSRAM Operation Mode should be added here if needed */
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//------------------------------------------Get the timing tuning config-----------------------------------------------//
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#ifdef SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
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//FLASH needs tuning, and it expects this core clock: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
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#define SPI_TIMING_FLASH_NEEDS_TUNING 1
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#endif
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#ifdef SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
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//PSRAM needs tuning, and it expects this core clock: SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
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#define SPI_TIMING_PSRAM_NEEDS_TUNING 1
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#endif
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//If both FLASH and PSRAM need tuning, the core clock should be same
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#if SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
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_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported");
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#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
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//If only FLASH needs tuning, the core clock could be as FLASH expected
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#elif SPI_TIMING_FLASH_NEEDS_TUNING && !SPI_TIMING_PSRAM_NEEDS_TUNING
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#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
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//If only PSRAM needs tuning, the core clock could be as PSRAM expected
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#elif !SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
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#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
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#else
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#define SPI_TIMING_CORE_CLOCK_MHZ 80
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#endif
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//------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------//
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#define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
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(spi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
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.available_config_num = MSPI_TIMING_##type##_CONFIG_NUM_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
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.default_config_id = MSPI_TIMING_##type##_DEFAULT_CONFIG_ID_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode }
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#define _GET_TUNING_CONFIG(type, core_clock, module_clock, mode) __GET_TUNING_CONFIG(type, core_clock, module_clock, mode)
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#define SPI_TIMING_FLASH_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(FLASH, core_clock_mhz, module_clock_mhz, mode)
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#define SPI_TIMING_PSRAM_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(PSRAM, core_clock_mhz, module_clock_mhz, mode)
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/**
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* SPI timing tuning registers. The macro `SPI_TIMING_FLASH_CONFIG_TABLE` below is the corresponding register value table.
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* Upper layer rely on these 3 registers to tune the timing.
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*/
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typedef struct {
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uint8_t spi_din_mode; /*!< input signal delay mode*/
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uint8_t spi_din_num; /*!< input signal delay number */
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uint8_t extra_dummy_len; /*!< extra dummy length*/
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} spi_timing_tuning_param_t;
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typedef struct {
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spi_timing_tuning_param_t tuning_config_table[SPI_TIMING_CONFIG_NUM_DEFAULT]; //available timing tuning configs
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uint32_t available_config_num;
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uint32_t default_config_id; //If tuning fails, we use this one as default
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} spi_timing_config_t;
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/**
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* The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock:
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*
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* PLL ----| |---- FLASH Module Clock
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* XTAL ----|----> Core Clock ---->|
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* RTC8M ----| |---- PSRAM Module Clock
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*
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*/
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typedef enum {
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SPI_TIMING_CONFIG_CORE_CLOCK_80M,
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SPI_TIMING_CONFIG_CORE_CLOCK_120M,
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SPI_TIMING_CONFIG_CORE_CLOCK_160M,
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SPI_TIMING_CONFIG_CORE_CLOCK_240M
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} spi_timing_config_core_clock_t;
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spi_timing_config_core_clock_t spi_timing_config_get_core_clock(void);
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void spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock);
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void spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv);
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void spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num);
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void spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy);
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void spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len);
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void spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv);
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void spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num);
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void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy);
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void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len);
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void spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t *buf, uint32_t addr, uint32_t len);
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#ifdef __cplusplus
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}
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#endif
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