Angus Gratton 1fc288556c esp_system: Reconfigure the WDTs at the start of the panic handler
This is mostly important on ESP32 ECO3 with the
ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core
before we disable the TG1 WDT then the first CPU can get stuck
in WDT ISR handle_livelock_int routine waiting for the other CPU.
2021-07-06 09:59:39 +08:00
..
2021-05-20 14:32:47 +10:00
2020-11-13 07:49:11 +11:00
2021-02-02 20:25:50 +08:00
2021-01-19 11:17:18 +08:00