mirror of
https://github.com/espressif/esp-idf.git
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216 lines
8.7 KiB
C
216 lines
8.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "ets_sys.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include "esp_assert.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/reset_reasons.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup rtc_apis, rtc registers and memory related apis
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* @brief rtc apis
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*/
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/** @addtogroup rtc_apis
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* @{
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*/
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/**************************************************************************************
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* Note: *
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* Some Rtc memory and registers are used, in ROM or in internal library. *
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* Please do not use reserved or used rtc memory or registers. *
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* *
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*************************************************************************************
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* RTC Memory & Store Register usage
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*************************************************************************************
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* rtc memory addr type size usage
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* 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
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* 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
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*
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* 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
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*
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*************************************************************************************
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* RTC store registers usage
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* RTC_CNTL_STORE0_REG RTC fix us, high 32 bits
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* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
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* RTC_CNTL_STORE2_REG Boot time, low word
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* RTC_CNTL_STORE3_REG Boot time, high word
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* RTC_CNTL_STORE4_REG External XTAL frequency
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* RTC_CNTL_STORE5_REG APB bus frequency
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* RTC_CNTL_STORE6_REG rtc reset cause
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* RTC_CNTL_STORE7_REG RTC fix us, low 32 bits
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*************************************************************************************
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*
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* Since esp32c2 does not support RTC fast mem, so use RTC store regs to record rtc time:
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*
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* |------------------------|----------------------------------------|
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* | RTC_CNTL_STORE0_REG | RTC_CNTL_STORE7_REG |
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* | rtc_fix_us(MSB) | rtc_fix_us(LSB) |
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* |------------------------|----------------------------------------|
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*/
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#define RTC_FIX_US_HIGH_REG RTC_CNTL_STORE0_REG
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#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
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#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
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#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
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#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
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#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
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#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
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#define RTC_FIX_US_LOW_REG RTC_CNTL_STORE7_REG
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#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
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typedef enum {
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AWAKE = 0, //<CPU ON
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LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
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DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
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} SLEEP_MODE;
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typedef enum {
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NO_MEAN = 0,
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POWERON_RESET = 1, /**<1, Vbat power on reset*/
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RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
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DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
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TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
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RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
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INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
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TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
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RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
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RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
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RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
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RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
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SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
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GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
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EFUSE_RESET = 20, /**<20, efuse reset digital core*/
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JTAG_RESET = 24, /**<24, jtag reset CPU*/
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} RESET_REASON;
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// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
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ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
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ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
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ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
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ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
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ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
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typedef enum {
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NO_SLEEP = 0,
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EXT_EVENT0_TRIG = BIT0,
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EXT_EVENT1_TRIG = BIT1,
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GPIO_TRIG = BIT2,
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TIMER_EXPIRE = BIT3,
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SDIO_TRIG = BIT4,
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MAC_TRIG = BIT5,
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UART0_TRIG = BIT6,
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UART1_TRIG = BIT7,
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SAR_TRIG = BIT9,
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BT_TRIG = BIT10,
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RISCV_TRIG = BIT11,
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XTAL_DEAD_TRIG = BIT12,
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RISCV_TRAP_TRIG = BIT13
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} WAKEUP_REASON;
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typedef enum {
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DISEN_WAKEUP = NO_SLEEP,
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EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
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EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
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GPIO_TRIG_EN = GPIO_TRIG,
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TIMER_EXPIRE_EN = TIMER_EXPIRE,
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SDIO_TRIG_EN = SDIO_TRIG,
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MAC_TRIG_EN = MAC_TRIG,
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UART0_TRIG_EN = UART0_TRIG,
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UART1_TRIG_EN = UART1_TRIG,
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SAR_TRIG_EN = SAR_TRIG,
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BT_TRIG_EN = BT_TRIG,
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RISCV_TRIG_EN = RISCV_TRIG,
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XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
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RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG
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} WAKEUP_ENABLE;
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/**
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* @brief Get the reset reason for CPU.
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*
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* @param int cpu_no : CPU no.
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*
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* @return RESET_REASON
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*/
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RESET_REASON rtc_get_reset_reason(int cpu_no);
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/**
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* @brief Get the wakeup cause for CPU.
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*
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* @param int cpu_no : CPU no.
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*
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* @return WAKEUP_REASON
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*/
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WAKEUP_REASON rtc_get_wakeup_cause(void);
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/**
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* @brief Suppress ROM log by setting specific RTC control register.
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* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
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*
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* @param None
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*
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* @return None
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*/
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static inline void rtc_suppress_rom_log(void)
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{
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/* To disable logging in the ROM, only the least significant bit of the register is used,
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* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
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* you need to write to this register in the same format.
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* Namely, the upper 16 bits and lower should be the same.
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*/
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REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
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}
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/**
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* @brief Software Reset digital core.
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*
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* It is not recommended to use this function in esp-idf, use
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* esp_restart() instead.
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*
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* @param None
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*
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* @return None
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*/
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void software_reset(void);
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/**
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* @brief Software Reset digital core.
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*
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* It is not recommended to use this function in esp-idf, use
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* esp_restart() instead.
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*
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* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
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*
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* @return None
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*/
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void software_reset_cpu(int cpu_no);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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