mirror of
https://github.com/espressif/esp-idf.git
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377 lines
12 KiB
C
377 lines
12 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Registers */
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/** Type of out register
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* LP_GPIO output register
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*/
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typedef union {
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struct {
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/** out_data_orig : R/W/WTC; bitpos: [6:0]; default: 0;
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* Configures the output value of LP_GPIO0 ~ 6 output in simple LP_GPIO output mode.\\
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* 0: Low level\\
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* 1: High level\\
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* The value of bit0 ~ bit6 correspond to the output value of LP_GPIO0 ~ LP_GPIO6
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* respectively. Bit7 ~ bit31 are invalid.\\
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*/
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uint32_t out_data_orig:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_out_reg_t;
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/** Type of out_w1ts register
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* LP_GPIO output set register
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*/
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typedef union {
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struct {
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/** out_w1ts : WT; bitpos: [6:0]; default: 0;
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* Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~
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* LP_GPIO6.\\
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* 0: Not set\\
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* 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1\\
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* Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\
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* Recommended operation: use this register to set LP_GPIO_OUT_REG. \\
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*/
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uint32_t out_w1ts:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_out_w1ts_reg_t;
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/** Type of out_w1tc register
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* LP_GPIO output clear register
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*/
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typedef union {
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struct {
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/** out_w1tc : WT; bitpos: [6:0]; default: 0;
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* Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0
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* ~ LP_GPIO6 output.\\
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* 0: Not clear\\
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* 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared.\\
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* Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\
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* Recommended operation: use this register to clear LP_GPIO_OUT_REG. \\
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*/
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uint32_t out_w1tc:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_out_w1tc_reg_t;
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/** Type of enable register
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* LP_GPIO output enable register
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*/
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typedef union {
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struct {
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/** enable_data : R/W/WTC; bitpos: [6:0]; default: 0;
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* Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO6.\\
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* 0: Not enable\\
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* 1: Enable\\
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* Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.\\
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*/
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uint32_t enable_data:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_enable_reg_t;
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/** Type of enable_w1ts register
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* LP_GPIO output enable set register
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*/
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typedef union {
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struct {
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/** enable_w1ts : WT; bitpos: [6:0]; default: 0;
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* Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of
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* LP_GPIO0 ~ LP_GPIO6.\\
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* 0: Not set\\
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* 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1\\
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* Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\
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* Recommended operation: use this register to set LP_GPIO_ENABLE_REG.\\
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*/
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uint32_t enable_w1ts:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_enable_w1ts_reg_t;
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/** Type of enable_w1tc register
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* LP_GPIO output enable clear register
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*/
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typedef union {
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struct {
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/** enable_w1tc : WT; bitpos: [6:0]; default: 0;
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* Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of
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* LP_GPIO0 ~ LP_GPIO6. \\
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* 0: Not clear\\
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* 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared\\
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* Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\
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* Recommended operation: use this register to clear LP_GPIO_ENABLE_REG.\\
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*/
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uint32_t enable_w1tc:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_enable_w1tc_reg_t;
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/** Type of in register
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* LP_GPIO input register
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*/
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typedef union {
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struct {
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/** in_data_next : RO; bitpos: [6:0]; default: 0;
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* Represents the input value of LP_GPIO0 ~ LP_GPIO6. Each bit represents a pin input
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* value:\\
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* 0: Low level\\
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* 1: High level\\
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* Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.\\
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*/
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uint32_t in_data_next:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_in_reg_t;
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/** Group: Interrupt Status Registers */
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/** Type of status register
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* LP_GPIO interrupt status register
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*/
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typedef union {
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struct {
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/** status_interrupt : R/W/WTC; bitpos: [6:0]; default: 0;
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* The interrupt status of LP_GPIO0 ~ LP_GPIO6, can be configured by the software.
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*
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* - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.
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* - Each bit represents the status of its corresponding LP_GPIO:
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*
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* - 0: Represents the LP_GPIO does not generate the interrupt configured by
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* LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
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* - 1: Represents the LP_GPIO generates the interrupt configured by
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* LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software.
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*
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*/
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uint32_t status_interrupt:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_status_reg_t;
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/** Type of status_w1ts register
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* LP_GPIO interrupt status set register
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*/
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typedef union {
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struct {
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/** status_w1ts : WT; bitpos: [6:0]; default: 0;
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* Configures whether or not to set the interrupt status register
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* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO6.
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*
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* - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
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* register to set LP_GPIO_STATUS_INTERRUPT.
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*/
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uint32_t status_w1ts:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_status_w1ts_reg_t;
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/** Type of status_w1tc register
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* LP_GPIO interrupt status clear register
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*/
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typedef union {
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struct {
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/** status_w1tc : WT; bitpos: [6:0]; default: 0;
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* Configures whether or not to clear the interrupt status register
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* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO6.
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*
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* - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
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* register to clear LP_GPIO_STATUS_INTERRUPT.
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*/
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uint32_t status_w1tc:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_status_w1tc_reg_t;
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/** Type of status_next register
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* LP_GPIO interrupt source register
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*/
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typedef union {
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struct {
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/** status_interrupt_next : RO; bitpos: [6:0]; default: 0;
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* Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO6.\\
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* Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.
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* Each bit represents:\\
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* 0: The LP_GPIO does not generate the interrupt configured by
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* LP_GPIO_PIN$n_INT_TYPE.\\
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* 1: The LP_GPIO generates an interrupt configured by LP_GPIO_PIN$n_INT_TYPE.\\
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* The interrupt could be rising edge interrupt, falling edge interrupt, level
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* sensitive interrupt and any edge interrupt.\\
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*/
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uint32_t status_interrupt_next:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} lp_gpio_status_next_reg_t;
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/** Group: Pin Configuration Registers */
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/** Type of pinn register
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* LP_GPIO0 configuration register
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*/
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typedef union {
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struct {
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/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
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* MUX operating clock for the second-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync2_bypass:2;
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/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
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* Configures to select pin drive mode. \\
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* 0: Normal output\\
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* 1: Open drain output \\
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*/
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uint32_t pinn_pad_driver:1;
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/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
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* MUX operating clock for the first-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync1_bypass:2;
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/** pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0;
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* LP_GPIO wakeup clear register.
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*/
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uint32_t pinn_edge_wakeup_clr:1;
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uint32_t reserved_6:1;
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/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
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* Configures LP_GPIO interrupt type.\\
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* 0: LP_GPIO interrupt disabled\\
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* 1: Rising edge trigger\\
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* 2: Falling edge trigger\\
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* 3: Any edge trigger\\
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* 4: Low level trigger\\
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* 5: High level trigger\\
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*/
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uint32_t pinn_int_type:3;
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/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
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* Configures whether or not to enable LP_GPIO wake-up function.\\
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* 0: Disable\\
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* 1: Enable\\
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* This function only wakes up the CPU from Light-sleep. \\
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*/
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uint32_t pinn_wakeup_enable:1;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} lp_gpio_pinn_reg_t;
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/** Group: Output Configuration Registers */
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/** Type of funcn_out_sel_cfg register
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* Configuration register for LP_GPIOn output
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*/
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typedef union {
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struct {
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/** funcn_out_inv_sel : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to invert the output value.\\
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* 0: Not invert\\
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* 1: Invert\\
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*/
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uint32_t funcn_out_inv_sel:1;
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uint32_t reserved_1:1;
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/** funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0;
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* Configures whether or not to invert the output enable signal.\\
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* 0: Not invert\\
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* 1: Invert\\
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*/
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uint32_t funcn_oe_inv_sel:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} lp_gpio_funcn_out_sel_cfg_reg_t;
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/** Group: Clock Gate Register */
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/** Type of clock_gate register
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* LP_GPIO clock gate register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* Configures whether or not to enable clock gate.\\
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* 0: Not enable\\
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* 1: Enable, the clock is free running. \\
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} lp_gpio_clock_gate_reg_t;
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/** Group: Version Register */
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/** Type of date register
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* LP_GPIO version register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 36766272;
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* Version control register. \\
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} lp_gpio_date_reg_t;
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typedef struct {
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uint32_t reserved_000;
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volatile lp_gpio_out_reg_t out;
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volatile lp_gpio_out_w1ts_reg_t out_w1ts;
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volatile lp_gpio_out_w1tc_reg_t out_w1tc;
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volatile lp_gpio_enable_reg_t enable;
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volatile lp_gpio_enable_w1ts_reg_t enable_w1ts;
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volatile lp_gpio_enable_w1tc_reg_t enable_w1tc;
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volatile lp_gpio_in_reg_t in;
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volatile lp_gpio_status_reg_t status;
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volatile lp_gpio_status_w1ts_reg_t status_w1ts;
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volatile lp_gpio_status_w1tc_reg_t status_w1tc;
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volatile lp_gpio_status_next_reg_t status_next;
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volatile lp_gpio_pinn_reg_t pinn[7];
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uint32_t reserved_04c[153];
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volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[7];
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uint32_t reserved_2cc[75];
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volatile lp_gpio_clock_gate_reg_t clock_gate;
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volatile lp_gpio_date_reg_t date;
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} lp_gpio_dev_t;
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extern lp_gpio_dev_t LP_GPIO;
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#ifndef __cplusplus
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_Static_assert(sizeof(lp_gpio_dev_t) == 0x400, "Invalid size of lp_gpio_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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