mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
40be44f827
- move .tbss to NOLOAD section - remove xtensa-specific entities from riscv scripts - explicit eh_frame terminator instead of "align magic" - 80 characters line length limit - refactor comments - discard .rela sections (the rela data will go to relates sections)
481 lines
13 KiB
Plaintext
481 lines
13 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "ld.common"
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/**
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* Added to maintain compatibility: there is no iram0 data section to place
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* _coredump_iram_XXX symbols that are defined in espcoredump's linker.lf
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*/
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_coredump_iram_start = 0;
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_coredump_iram_end = 0;
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/* Default entry point */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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/**
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* RTC fast memory holds RTC wake stub code,
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* including from any source file named rtc_wake_stub*.c
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*/
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.rtc.text :
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{
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ALIGNED_SYMBOL(4, _rtc_text_start)
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mapping[rtc_text]
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*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
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/* Padding for possible CPU prefetch + alignment for PMS split lines */
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. += _esp_memprot_prefetch_pad_size;
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. = ALIGN(_esp_memprot_align_size);
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_rtc_text_end = ABSOLUTE(.);
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} > rtc_iram_seg
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/**
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* This section is required to skip rtc.text area because rtc_iram_seg and
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* rtc_data_seg are reflect the same address space on different buses.
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*/
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.rtc.dummy :
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{
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_rtc_dummy_start = ABSOLUTE(.);
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_rtc_fast_start = ABSOLUTE(.);
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. = SIZEOF(.rtc.text);
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_rtc_dummy_end = ABSOLUTE(.);
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} > rtc_data_seg
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/**
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* This section located in RTC FAST Memory area.
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* It holds data marked with RTC_FAST_ATTR attribute.
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* See the file "esp_attr.h" for more information.
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*/
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.rtc.force_fast :
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{
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ALIGNED_SYMBOL(4, _rtc_force_fast_start)
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mapping[rtc_force_fast]
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*(.rtc.force_fast .rtc.force_fast.*)
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ALIGNED_SYMBOL(4, _rtc_force_fast_end)
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} > rtc_data_seg
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/**
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* RTC data section holds RTC wake stub
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* data/rodata, including from any source file
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* named rtc_wake_stub*.c and the data marked with
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* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
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* The memory location of the data is dependent on
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* CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM option.
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*/
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.rtc.data :
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{
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_rtc_data_start = ABSOLUTE(.);
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mapping[rtc_data]
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*rtc_wake_stub*.*(.data .rodata .data.* .rodata.*)
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_rtc_data_end = ABSOLUTE(.);
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} > rtc_data_location
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/* RTC bss, from any source file named rtc_wake_stub*.c */
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.rtc.bss (NOLOAD) :
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{
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_rtc_bss_start = ABSOLUTE(.);
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*rtc_wake_stub*.*(.bss .bss.*)
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*rtc_wake_stub*.*(COMMON)
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mapping[rtc_bss]
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_rtc_bss_end = ABSOLUTE(.);
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} > rtc_data_location
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/**
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* This section holds data that should not be initialized at power up
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* and will be retained during deep sleep.
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* User data marked with RTC_NOINIT_ATTR will be placed
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* into this section. See the file "esp_attr.h" for more information.
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* The memory location of the data is dependent on
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* CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM option.
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*/
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.rtc_noinit (NOLOAD):
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{
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ALIGNED_SYMBOL(4, _rtc_noinit_start)
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*(.rtc_noinit .rtc_noinit.*)
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ALIGNED_SYMBOL(4, _rtc_noinit_end)
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} > rtc_data_location
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/**
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* This section located in RTC SLOW Memory area.
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* It holds data marked with RTC_SLOW_ATTR attribute.
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* See the file "esp_attr.h" for more information.
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*/
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.rtc.force_slow :
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{
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ALIGNED_SYMBOL(4, _rtc_force_slow_start)
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*(.rtc.force_slow .rtc.force_slow.*)
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ALIGNED_SYMBOL(4, _rtc_force_slow_end)
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} > rtc_slow_seg
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/**
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* This section holds RTC data that should have fixed addresses.
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* The data are not initialized at power-up and are retained during deep
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* sleep.
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*/
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.rtc_reserved (NOLOAD):
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{
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ALIGNED_SYMBOL(4, _rtc_reserved_start)
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/**
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* New data can only be added here to ensure existing data are not moved.
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* Because data have adhered to the end of the segment and code is relied
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* on it.
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* >> put new data here <<
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*/
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*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
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KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
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_rtc_reserved_end = ABSOLUTE(.);
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} > rtc_reserved_seg
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_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
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ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
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"RTC reserved segment data does not fit.")
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/* Get size of rtc slow data based on rtc_data_location alias */
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_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_slow_end - _rtc_data_start)
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: (_rtc_force_slow_end - _rtc_force_slow_start);
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_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_fast_end - _rtc_fast_start)
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: (_rtc_noinit_end - _rtc_fast_start);
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ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
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"RTC_SLOW segment data does not fit.")
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ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
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"RTC_FAST segment data does not fit.")
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/* Send .iram0 code to iram */
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.iram0.vectors :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to IRAM */
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_vector_table = ABSOLUTE(.);
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. = 0x0;
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KEEP(*(.WindowVectors.text));
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. = 0x180;
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KEEP(*(.Level2InterruptVector.text));
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. = 0x1c0;
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KEEP(*(.Level3InterruptVector.text));
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. = 0x200;
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KEEP(*(.Level4InterruptVector.text));
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. = 0x240;
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KEEP(*(.Level5InterruptVector.text));
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. = 0x280;
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KEEP(*(.DebugExceptionVector.text));
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. = 0x2c0;
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KEEP(*(.NMIExceptionVector.text));
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. = 0x300;
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KEEP(*(.KernelExceptionVector.text));
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. = 0x340;
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KEEP(*(.UserExceptionVector.text));
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. = 0x3C0;
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KEEP(*(.DoubleExceptionVector.text));
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. = 0x400;
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_invalid_pc_placeholder = ABSOLUTE(.);
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*(.*Vector.literal)
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*(.UserEnter.literal);
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*(.UserEnter.text);
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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_init_end = ABSOLUTE(.);
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} > iram0_0_seg
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.iram0.text :
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{
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/* Code marked as running out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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mapping[iram0_text]
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/* Padding for possible CPU prefetch + alignment for PMS split lines */
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. += _esp_memprot_prefetch_pad_size;
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. = ALIGN(_esp_memprot_align_size);
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/* iram_end_test section exists for use by memprot unit tests only */
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*(.iram_end_test)
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_iram_text_end = ABSOLUTE(.);
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} > iram0_0_seg
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.dram0_reserved_for_iram (NOLOAD):
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{
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. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
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} > dram0_0_seg
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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mapping[dram0_data]
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_data_end = ABSOLUTE(.);
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} > dram0_0_seg
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/**
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* This section holds data that should not be initialized at power up.
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* The section located in Internal SRAM memory region. The macro _NOINIT
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* can be used as attribute to place data into this section.
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* See the "esp_attr.h" file for more information.
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*/
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.noinit (NOLOAD):
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{
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ALIGNED_SYMBOL(4, _noinit_start)
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*(.noinit .noinit.*)
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ALIGNED_SYMBOL(4, _noinit_end)
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} > dram0_0_seg
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/* External Memory BSS. (Variables with EXT_RAM_BSS_ATTR attribute). */
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.ext_ram.bss (NOLOAD) :
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{
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ALIGNED_SYMBOL(4, _ext_ram_bss_start)
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mapping[extern_ram]
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ALIGNED_SYMBOL(4, _ext_ram_bss_end)
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} > extern_ram_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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ALIGNED_SYMBOL(8, _bss_start)
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/**
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* ldgen places all bss-related data to mapping[dram0_bss]
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* (See components/esp_system/app.lf).
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*/
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mapping[dram0_bss]
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ALIGNED_SYMBOL(8, _bss_end)
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} > dram0_0_seg
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.flash.appdesc : ALIGN(0x10)
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{
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/**
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* Mark flash.rodata start.
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* This can be used for mmu driver to maintain virtual address
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*/
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_rodata_reserved_start = ABSOLUTE(.);
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_rodata_start = ABSOLUTE(.);
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/* !DO NOT PUT ANYTHING BEFORE THIS! */
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/* Should be the first. App version info. */
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*(.rodata_desc .rodata_desc.*)
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/* Should be the second. Custom app version info. */
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*(.rodata_custom_desc .rodata_custom_desc.*)
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/**
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* Create an empty gap within this section. Thanks to this, the end of this
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* section will match .flah.rodata's begin address. Thus, both sections
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* will be merged when creating the final bin image.
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*/
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. = ALIGN(ALIGNOF(.flash.rodata));
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} > default_rodata_seg
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ASSERT_SECTIONS_GAP(.flash.appdesc, .flash.rodata)
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.flash.rodata : ALIGN(0x10)
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{
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_flash_rodata_start = ABSOLUTE(.);
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mapping[flash_rodata]
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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/* C++ exception handlers table. */
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ALIGNED_SYMBOL(4, __XT_EXCEPTION_TABLE_)
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*(.xt_except_table)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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ALIGNED_SYMBOL(4, __XT_EXCEPTION_DESCS_)
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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ALIGNED_SYMBOL(4, __eh_frame)
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KEEP(*(.eh_frame))
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/**
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* As we are not linking with crtend.o, which includes the CIE terminator
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* (see __FRAME_END__ in libgcc sources), it is manually provided here.
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*/
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LONG(0);
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/**
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* C++ constructor tables.
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*
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* Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt.
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*/
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ALIGNED_SYMBOL(4, __init_array_start)
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*)))
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__init_array_end = ABSOLUTE(.);
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/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
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ALIGNED_SYMBOL(4, soc_reserved_memory_region_start)
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KEEP (*(.reserved_memory_address))
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soc_reserved_memory_region_end = ABSOLUTE(.);
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/* System init functions registered via ESP_SYSTEM_INIT_FN */
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ALIGNED_SYMBOL(4, _esp_system_init_fn_array_start)
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KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
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_esp_system_init_fn_array_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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/* TLS data. */
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ALIGNED_SYMBOL(4, _thread_local_start)
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*(.tdata)
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*(.tdata.*)
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*(.tbss)
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*(.tbss.*)
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_thread_local_end = ABSOLUTE(.);
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} > default_rodata_seg
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_flash_rodata_align = ALIGNOF(.flash.rodata);
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/**
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* This section contains all the rodata that is not used
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* at runtime, helping to avoid an increase in binary size.
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*/
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.flash.rodata_noload (NOLOAD) :
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{
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/**
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* This symbol marks the end of flash.rodata. It can be utilized by the MMU
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* driver to maintain the virtual address.
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* NOLOAD rodata may not be included in this section.
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*/
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_rodata_reserved_end = ABSOLUTE(.);
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mapping[rodata_noload]
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} > default_rodata_seg
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.flash.text :
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{
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_stext = .;
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/**
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* Mark the start of flash.text.
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* This can be used by the MMU driver to maintain the virtual address.
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*/
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_instruction_reserved_start = ABSOLUTE(.);
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_text_start = ABSOLUTE(.);
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mapping[flash_text]
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*(.stub)
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*(.gnu.warning)
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*(.gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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/**
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* CPU will try to prefetch up to 16 bytes of of instructions.
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* This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction,
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* add dummy bytes to ensure this.
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*/
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. += _esp_flash_mmap_prefetch_pad_size;
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_text_end = ABSOLUTE(.);
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/**
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* Mark the flash.text end.
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* This can be used for MMU driver to maintain virtual address.
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*/
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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/**
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* Similar to _iram_start, this symbol goes here so it is
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* resolved by addr2line in preference to the first symbol in
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* the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} > default_code_seg
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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ALIGNED_SYMBOL(4, _iram_end)
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} > iram0_0_seg
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/* Marks the end of data, bss and possibly rodata */
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.dram0.heap_start (NOLOAD) :
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{
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/* Lowest possible start address for the heap */
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ALIGNED_SYMBOL(8, _heap_low_start)
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} > dram0_0_seg
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/**
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* This section will be used by the debugger and disassembler to get more
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* information about raw data present in the code.
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* Indeed, it may be required to add some padding at some points in the code
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* in order to align a branch/jump destination on a particular bound.
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* Padding these instructions will generate null bytes that shall be
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* interpreted as data, and not code by the debugger or disassembler.
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* This section will only be present in the ELF file, not in the final binary
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* For more details, check GCC-212
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*/
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.xt.prop 0 :
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{
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KEEP (*(.xt.prop .gnu.linkonce.prop.*))
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}
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.xt.lit 0 :
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{
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KEEP (*(.xt.lit .gnu.linkonce.p.*))
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}
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}
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ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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"IRAM0 segment data does not fit.")
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ASSERT(((_heap_low_start - _data_start) <= LENGTH(dram0_0_seg)),
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"DRAM segment data does not fit.")
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