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602 lines
18 KiB
C
602 lines
18 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,7], rx_channel = [0,7]
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "hal/misc.h"
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#include "hal/assert.h"
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#include "soc/rmt_struct.h"
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#include "hal/rmt_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RMT_LL_EVENT_TX_DONE(channel) (1 << ((channel) * 3))
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#define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 24))
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#define RMT_LL_EVENT_TX_LOOP_END(channel) (0) // esp32 doesn't support tx loop count
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#define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) * 3 + 2))
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#define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) * 3 + 1))
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#define RMT_LL_EVENT_RX_THRES(channel) (0) // esp32 doesn't support rx wrap
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#define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) * 3 + 2))
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#define RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) | RMT_LL_EVENT_TX_LOOP_END(channel))
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#define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(channel))
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typedef enum {
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RMT_LL_MEM_OWNER_SW = 0,
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RMT_LL_MEM_OWNER_HW = 1,
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} rmt_ll_mem_owner_t;
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/**
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* @brief Enable clock gate for register and memory
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*
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* @param dev Peripheral instance address
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
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{
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dev->conf_ch[0].conf0.clk_en = enable; // register clock gating
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}
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/**
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* @brief Power down memory
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*
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* @param dev Peripheral instance address
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* @param enable True to power down, False to power up
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*/
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static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
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{
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dev->conf_ch[0].conf0.mem_pd = enable; // Only conf0 register of channel0 has `mem_pd`
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}
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/**
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* @brief Enable APB accessing RMT memory in nonfifo mode
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*
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* @param dev Peripheral instance address
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_enable_mem_access_nonfifo(rmt_dev_t *dev, bool enable)
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{
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dev->apb_conf.fifo_mask = enable;
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}
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/**
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* @brief Set clock source and divider for RMT channel group
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*
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* @param dev Peripheral instance address
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* @param channel not used as clock source is set for all channels
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* @param src Clock source
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* @param divider_integral Integral part of the divider
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* @param divider_denominator Denominator part of the divider
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* @param divider_numerator Numerator part of the divider
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*/
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static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t src,
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uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
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{
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(void)divider_integral;
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(void)divider_denominator;
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(void)divider_numerator;
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switch (src) {
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case RMT_CLK_SRC_APB:
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dev->conf_ch[channel].conf1.ref_always_on = 1;
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break;
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case RMT_CLK_SRC_REF_TICK:
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dev->conf_ch[channel].conf1.ref_always_on = 0;
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break;
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default:
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HAL_ASSERT(false && "unsupported RMT clock source");
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break;
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}
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}
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////////////////////////////////////////TX Channel Specific/////////////////////////////////////////////////////////////
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/**
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* @brief Reset clock divider for TX channels by mask
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*
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* @param dev Peripheral instance address
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* @param channel_mask Mask of TX channels
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*/
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static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask)
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{
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for (int i = 0; i < 8; i++) {
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if (channel_mask & (1 << i)) {
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dev->conf_ch[i].conf1.ref_cnt_rst = 1;
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}
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}
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}
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/**
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* @brief Set TX channel clock divider
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param div Division value
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*/
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static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
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{
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HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range");
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// limit the maximum divider to 256
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if (div >= 256) {
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div = 0; // 0 means 256 division
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
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}
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/**
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* @brief Reset RMT reading pointer for TX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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*/
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static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->conf_ch[channel].conf1.mem_rd_rst = 1;
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dev->conf_ch[channel].conf1.mem_rd_rst = 0;
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dev->conf_ch[channel].conf1.apb_mem_rst = 1;
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dev->conf_ch[channel].conf1.apb_mem_rst = 0;
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}
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/**
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* @brief Start transmitting for TX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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*/
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static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
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{
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dev->conf_ch[channel].conf1.tx_start = 1;
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}
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/**
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* @brief Set memory block number for TX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param block_num memory block number
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*/
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static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
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{
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dev->conf_ch[channel].conf0.mem_size = block_num;
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}
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/**
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* @brief Enable TX wrap
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->apb_conf.mem_tx_wrap_en = enable;
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}
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/**
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* @brief Enable transmitting in a loop
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf1.tx_conti_mode = enable;
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}
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/**
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* @brief Fix the output level when TX channel is in IDLE state
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param level IDLE level (1 => high, 0 => low)
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* @param enable True to fix the IDLE level, otherwise the IDLE level is determined by EOF encoder
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*/
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static inline void rmt_ll_tx_fix_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level, bool enable)
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{
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dev->conf_ch[channel].conf1.idle_out_en = enable;
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dev->conf_ch[channel].conf1.idle_out_lv = level;
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}
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/**
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* @brief Set the amount of RMT symbols that can trigger the limitation interrupt
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param limit Specify the number of symbols
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*/
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static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
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{
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dev->tx_lim_ch[channel].limit = limit;
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}
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/**
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* @brief Set high and low duration of carrier signal
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param high_ticks Duration of high level
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* @param low_ticks Duration of low level
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*/
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static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
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{
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HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks");
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// ticks=0 means 65536 in hardware
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if (high_ticks >= 65536) {
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high_ticks = 0;
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}
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if (low_ticks >= 65536) {
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low_ticks = 0;
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], high, high_ticks);
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], low, low_ticks);
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}
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/**
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* @brief Enable modulating carrier signal to TX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf0.carrier_en = enable;
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}
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/**
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* @brief Set on high or low to modulate the carrier signal
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @param level Which level to modulate on (0=>low level, 1=>high level)
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*/
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static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
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{
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dev->conf_ch[channel].conf0.carrier_out_lv = level;
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}
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////////////////////////////////////////RX Channel Specific/////////////////////////////////////////////////////////////
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/**
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* @brief Reset clock divider for RX channels by mask
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*
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* @param dev Peripheral instance address
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* @param channel_mask Mask of RX channels
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*/
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static inline void rmt_ll_rx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask)
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{
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for (int i = 0; i < 8; i++) {
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if (channel_mask & (1 << i)) {
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dev->conf_ch[i].conf1.ref_cnt_rst = 1;
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}
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}
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}
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/**
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* @brief Set RX channel clock divider
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @param div Division value
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*/
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static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
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{
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HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range");
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// limit the maximum divider to 256
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if (div >= 256) {
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div = 0; // 0 means 256 division
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
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}
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/**
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* @brief Reset RMT writing pointer for RX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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*/
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static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->conf_ch[channel].conf1.mem_wr_rst = 1;
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dev->conf_ch[channel].conf1.mem_wr_rst = 0;
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dev->conf_ch[channel].conf1.apb_mem_rst = 1;
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dev->conf_ch[channel].conf1.apb_mem_rst = 0;
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}
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/**
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* @brief Enable receiving for RX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf1.rx_en = enable;
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}
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/**
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* @brief Set memory block number for RX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @param block_num memory block number
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*/
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static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
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{
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dev->conf_ch[channel].conf0.mem_size = block_num;
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}
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/**
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* @brief Set the time length for RX channel before going into IDLE state
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @param thres Time length threshold
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*/
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static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);
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}
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/**
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* @brief Set RMT memory owner for RX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @param owner Memory owner
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*/
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static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt_ll_mem_owner_t owner)
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{
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dev->conf_ch[channel].conf1.mem_owner = owner;
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}
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/**
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* @brief Enable filter for RX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX chanenl number
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf_ch[channel].conf1.rx_filter_en = enable;
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}
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/**
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* @brief Set RX channel filter threshold (i.e. the maximum width of one pulse signal that would be treated as a noise)
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @param thres Filter threshold
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*/
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static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);
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}
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/**
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* @brief Get RMT memory write cursor offset
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @return writer offset
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*/
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static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32_t channel)
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{
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return (dev->status_ch[channel] & 0x3FF) - (channel) * 64;
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}
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//////////////////////////////////////////Interrupt Specific////////////////////////////////////////////////////////////
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/**
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* @brief Enable RMT interrupt for specific event mask
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*
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* @param dev Peripheral instance address
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* @param mask Event mask
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* @param enable True to enable, False to disable
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*/
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static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->int_ena.val |= mask;
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} else {
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dev->int_ena.val &= ~mask;
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}
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}
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/**
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* @brief Clear RMT interrupt status by mask
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*
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* @param dev Peripheral instance address
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* @param mask Interupt status mask
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*/
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static inline void rmt_ll_clear_interrupt_status(rmt_dev_t *dev, uint32_t mask)
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{
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dev->int_clr.val = mask;
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}
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/**
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* @brief Get interrupt status register address
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*
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* @param dev Peripheral instance address
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* @return Register address
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*/
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static inline volatile void *rmt_ll_get_interrupt_status_reg(rmt_dev_t *dev)
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{
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return &dev->int_st;
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}
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/**
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* @brief Get interrupt status for TX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @return Interrupt status
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*/
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static inline uint32_t rmt_ll_tx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->int_st.val & RMT_LL_EVENT_TX_MASK(channel);
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}
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/**
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* @brief Get interrupt raw status for TX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT TX channel number
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* @return Interrupt raw status
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*/
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static inline uint32_t rmt_ll_tx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->int_raw.val & (RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel));
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}
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/**
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* @brief Get interrupt raw status for RX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @return Interrupt raw status
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*/
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static inline uint32_t rmt_ll_rx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->int_raw.val & (RMT_LL_EVENT_RX_MASK(channel) | RMT_LL_EVENT_RX_ERROR(channel));
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}
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/**
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* @brief Get interrupt status for RX channel
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*
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* @param dev Peripheral instance address
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* @param channel RMT RX channel number
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* @return Interrupt status
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*/
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static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->int_st.val & RMT_LL_EVENT_RX_MASK(channel);
|
|
}
|
|
|
|
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
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|
/////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
|
|
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->status_ch[channel];
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->status_ch[channel];
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
|
|
return div == 0 ? 256 : div;
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
|
|
return div == 0 ? 256 : div;
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->conf_ch[channel].conf0.mem_size;
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->conf_ch[channel].conf0.mem_size;
|
|
}
|
|
|
|
static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->conf_ch[channel].conf1.tx_conti_mode;
|
|
}
|
|
|
|
static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
if (dev->conf_ch[channel].conf1.ref_always_on) {
|
|
return RMT_CLK_SRC_APB;
|
|
}
|
|
return RMT_CLK_SRC_REF_TICK;
|
|
}
|
|
|
|
static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->conf_ch[channel].conf1.idle_out_en;
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->conf_ch[channel].conf1.idle_out_lv;
|
|
}
|
|
|
|
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
|
|
{
|
|
// Only conf0 register of channel0 has `mem_pd`
|
|
return dev->conf_ch[0].conf0.mem_pd;
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
|
|
{
|
|
return dev->conf_ch[channel].conf1.mem_owner;
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
|
|
{
|
|
uint32_t status = dev->int_st.val;
|
|
return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6) |
|
|
((status & 0x1000) >> 8) | ((status & 0x8000) >> 10) | ((status & 0x40000) >> 12) | ((status & 0x200000) >> 14);
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
|
|
{
|
|
uint32_t status = dev->int_st.val;
|
|
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7) |
|
|
((status & 0x2000) >> 9) | ((status & 0x10000) >> 11) | ((status & 0x80000) >> 13) | ((status & 0x400000) >> 15);
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev)
|
|
{
|
|
uint32_t status = dev->int_st.val;
|
|
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8) |
|
|
((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 0x100000) >> 14) | ((status & 0x800000) >> 16);
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev)
|
|
{
|
|
uint32_t status = dev->int_st.val;
|
|
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8) |
|
|
((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 0x100000) >> 14) | ((status & 0x800000) >> 16);
|
|
}
|
|
|
|
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
|
|
{
|
|
uint32_t status = dev->int_st.val;
|
|
return (status & 0xFF000000) >> 24;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|