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38d54b4b62
Need to ensure that the cacheline being written back will not be accessed during the write back process.
85 lines
1.3 KiB
Plaintext
85 lines
1.3 KiB
Plaintext
#####################################################
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# This file is auto-generated from SoC caps
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# using gen_soc_caps_kconfig.py, do not edit manually
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#####################################################
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config ESP_ROM_HAS_CRC_LE
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bool
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default y
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config ESP_ROM_HAS_CRC_BE
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bool
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default y
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config ESP_ROM_HAS_MZ_CRC32
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bool
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default y
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config ESP_ROM_HAS_JPEG_DECODE
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bool
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default y
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config ESP_ROM_UART_CLK_IS_XTAL
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bool
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default y
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config ESP_ROM_HAS_RETARGETABLE_LOCKING
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bool
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default y
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config ESP_ROM_USB_SERIAL_DEVICE_NUM
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int
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default 4
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config ESP_ROM_HAS_ERASE_0_REGION_BUG
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bool
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default y
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config ESP_ROM_GET_CLK_FREQ
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bool
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default y
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config ESP_ROM_HAS_HAL_WDT
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bool
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default y
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config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
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bool
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default y
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config ESP_ROM_HAS_LAYOUT_TABLE
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bool
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default y
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config ESP_ROM_HAS_SPI_FLASH
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bool
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default y
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config ESP_ROM_HAS_ETS_PRINTF_BUG
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bool
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default y
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config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
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bool
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default y
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config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
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bool
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default y
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config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
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bool
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default y
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config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG
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bool
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default y
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config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
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bool
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default y
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config ESP_ROM_HAS_CACHE_WRITEBACK_BUG
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bool
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default y
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