mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
112 lines
3.2 KiB
C
112 lines
3.2 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/misc.h"
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#include "soc/dedic_gpio_struct.h"
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static inline void dedic_gpio_ll_enable_instruction_access_out(dedic_dev_t *dev, uint32_t channel_mask, bool enable)
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{
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if (enable) {
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dev->gpio_out_cpu.val |= channel_mask;
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} else {
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dev->gpio_out_cpu.val &= ~channel_mask;
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}
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}
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static inline void dedic_gpio_ll_write_all(dedic_dev_t *dev, uint32_t value)
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{
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dev->gpio_out_drt.val = value;
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}
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static inline void dedic_gpio_ll_write_mask(dedic_dev_t *dev, uint32_t channel_mask, uint32_t value)
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{
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dedic_gpio_out_msk_reg_t d = {
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.gpio_out_msk = channel_mask,
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.gpio_out_value = value
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};
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dev->gpio_out_msk.val = d.val;
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}
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static inline void dedic_gpio_ll_set_channel(dedic_dev_t *dev, uint32_t channel)
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{
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dev->gpio_out_idv.val = 1 << (2 * channel);
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}
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static inline void dedic_gpio_ll_clear_channel(dedic_dev_t *dev, uint32_t channel)
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{
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dev->gpio_out_idv.val = 2 << (2 * channel);
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}
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static inline void dedic_gpio_ll_toggle_channel(dedic_dev_t *dev, uint32_t channel)
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{
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dev->gpio_out_idv.val = 3 << (2 * channel);
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}
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static inline uint32_t dedic_gpio_ll_read_out_all(dedic_dev_t *dev)
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{
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return HAL_FORCE_READ_U32_REG_FIELD(dev->gpio_out_scan, gpio_out_status);
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}
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static inline uint32_t dedic_gpio_ll_read_in_all(dedic_dev_t *dev)
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{
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return HAL_FORCE_READ_U32_REG_FIELD(dev->gpio_in_scan, gpio_in_status);
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}
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static inline void dedic_gpio_ll_set_input_delay(dedic_dev_t *dev, uint32_t channel, uint32_t delay_cpu_clks)
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{
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dev->gpio_in_dly.val &= ~(3 << (2 * channel));
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dev->gpio_in_dly.val |= (delay_cpu_clks & 0x03) << (2 * channel);
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}
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static inline uint32_t dedic_gpio_ll_get_input_delay(dedic_dev_t *dev, uint32_t channel)
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{
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return (dev->gpio_in_dly.val & (3 << (2 * channel)) >> (2 * channel));
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}
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static inline void dedic_gpio_ll_set_interrupt_type(dedic_dev_t *dev, uint32_t channel, uint32_t type)
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{
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dev->gpio_intr_rcgn.val &= ~(7 << (3 * channel));
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dev->gpio_intr_rcgn.val |= (type & 0x07) << (3 * channel);
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}
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static inline void dedic_gpio_ll_enable_interrupt(dedic_dev_t *dev, uint32_t channel_mask, bool enable)
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{
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if (enable) {
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dev->gpio_intr_rls.val |= channel_mask;
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} else {
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dev->gpio_intr_rls.val &= ~channel_mask;
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}
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}
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static inline uint32_t __attribute__((always_inline)) dedic_gpio_ll_get_interrupt_status(dedic_dev_t *dev)
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{
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return dev->gpio_intr_st.val;
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}
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static inline void __attribute__((always_inline)) dedic_gpio_ll_clear_interrupt_status(dedic_dev_t *dev, uint32_t channel_mask)
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{
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dev->gpio_intr_clr.val = channel_mask;
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}
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#ifdef __cplusplus
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}
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#endif
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