mirror of
https://github.com/espressif/esp-idf.git
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a9fda54d39
This commit updates the visibility of various header files and cleans up some unnecessary inclusions. Also, this commit removes certain header include paths which were maintained for backward compatibility.
124 lines
3.6 KiB
C
124 lines
3.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freertos/FreeRTOS.h>
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#include "clk_ctrl_os.h"
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#include "esp_check.h"
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#include "sdkconfig.h"
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#define DELAY_RTC_CLK_SWITCH 5
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static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static uint8_t s_periph_ref_counts = 0;
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static uint32_t s_rtc_clk_freq = 0; // Frequency of the 8M/256 clock in Hz
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#if SOC_CLK_APLL_SUPPORTED
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static const char *TAG = "clk_ctrl_os";
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// Current APLL frequency, in HZ. Zero if APLL is not enabled.
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static uint32_t s_cur_apll_freq = 0;
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static int s_apll_ref_cnt = 0;
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#endif
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bool periph_rtc_dig_clk8m_enable(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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if (s_periph_ref_counts == 0) {
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rtc_dig_clk8m_enable();
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#if CONFIG_IDF_TARGET_ESP32H2
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s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_RC32K, 100));
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#else
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s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, 100));
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#endif
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if (s_rtc_clk_freq == 0) {
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portEXIT_CRITICAL(&periph_spinlock);
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return false;
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}
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}
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s_periph_ref_counts++;
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portEXIT_CRITICAL(&periph_spinlock);
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return true;
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}
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uint32_t periph_rtc_dig_clk8m_get_freq(void)
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{
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return s_rtc_clk_freq * 256;
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}
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void periph_rtc_dig_clk8m_disable(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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assert(s_periph_ref_counts > 0);
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s_periph_ref_counts--;
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if (s_periph_ref_counts == 0) {
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s_rtc_clk_freq = 0;
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rtc_dig_clk8m_disable();
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}
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portEXIT_CRITICAL(&periph_spinlock);
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}
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#if SOC_CLK_APLL_SUPPORTED
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void periph_rtc_apll_acquire(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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s_apll_ref_cnt++;
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if (s_apll_ref_cnt == 1) {
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// For the first time enable APLL, need to set power up
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rtc_clk_apll_enable(true);
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}
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portEXIT_CRITICAL(&periph_spinlock);
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}
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void periph_rtc_apll_release(void)
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{
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portENTER_CRITICAL(&periph_spinlock);
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assert(s_apll_ref_cnt > 0);
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s_apll_ref_cnt--;
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if (s_apll_ref_cnt == 0) {
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// If there is no peripheral using APLL, shut down the power
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s_cur_apll_freq = 0;
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rtc_clk_apll_enable(false);
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}
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portEXIT_CRITICAL(&periph_spinlock);
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}
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esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq, uint32_t *real_freq)
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{
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uint32_t o_div = 0;
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uint32_t sdm0 = 0;
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uint32_t sdm1 = 0;
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uint32_t sdm2 = 0;
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// Guarantee 'periph_rtc_apll_acquire' has been called before set apll freq
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assert(s_apll_ref_cnt > 0);
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uint32_t apll_freq = rtc_clk_apll_coeff_calc(expt_freq, &o_div, &sdm0, &sdm1, &sdm2);
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ESP_RETURN_ON_FALSE(apll_freq, ESP_ERR_INVALID_ARG, TAG, "APLL coefficients calculate failed");
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bool need_config = true;
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portENTER_CRITICAL(&periph_spinlock);
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/* If APLL is not in use or only one peripheral in use, its frequency can be changed as will
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* But when more than one peripheral refers APLL, its frequency is not allowed to change once it is set */
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if (s_cur_apll_freq == 0 || s_apll_ref_cnt < 2) {
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s_cur_apll_freq = apll_freq;
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} else {
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apll_freq = s_cur_apll_freq;
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need_config = false;
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}
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portEXIT_CRITICAL(&periph_spinlock);
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*real_freq = apll_freq;
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if (need_config) {
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ESP_LOGD(TAG, "APLL will working at %d Hz with coefficients [sdm0] %d [sdm1] %d [sdm2] %d [o_div] %d",
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apll_freq, sdm0, sdm1, sdm2, o_div);
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/* Set coefficients for APLL, notice that it doesn't mean APLL will start */
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rtc_clk_apll_coeff_set(o_div, sdm0, sdm1, sdm2);
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} else {
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return ESP_ERR_INVALID_STATE;
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}
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return ESP_OK;
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}
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#endif // SOC_I2S_SUPPORTS_APLL
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