mirror of
https://github.com/espressif/esp-idf.git
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369 lines
12 KiB
C
369 lines
12 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: configuration registers */
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/** Type of log_setting register
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* Bus access logging configuration register
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*/
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typedef union {
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struct {
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/** log_mode : R/W; bitpos: [3:0]; default: 0;
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* Configures monitoring modes.bit[0]: Configures write monitoring. \\
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* 0: Disable \\
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* 1: Enable\\
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* bit[1]: Configures word monitoring. \\
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* 0: Disable \\
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* 1: Enable\\
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* bit[2]: Configures halfword monitoring. \\
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* 0: Disable \\
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* 1: Enable\\
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* bit[3]: Configures byte monitoring. \\
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* 0: Disable \\
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* 1: Enable\\
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*/
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uint32_t log_mode:4;
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/** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
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* Configures the writing mode for recorded data.1: Loop mode\\
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* 0: Non-loop mode\\
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*/
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uint32_t log_mem_loop_enable:1;
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uint32_t reserved_5:3;
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/** log_core_ena : R/W; bitpos: [15:8]; default: 0;
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* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
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* enable HP CPU bus access logging. \\
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* 0: Disable \\
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* 1: Enable\\
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* Bit[7:1]: Reserved
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*/
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uint32_t log_core_ena:8;
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/** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
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* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
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* to enable DMA_0 bus access logging. \\
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* 0: Disable \\
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* 1: Enable\\
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* Bit[7:1]: Reserved
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*/
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uint32_t log_dma_0_ena:8;
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/** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
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* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
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* to enable DMA_1 bus access logging. \\
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* 0: Disable \\
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* 1: Enable\\
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* Bit[7:1]: Reserved
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*/
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uint32_t log_dma_1_ena:8;
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};
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uint32_t val;
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} mem_monitor_log_setting_reg_t;
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/** Type of log_setting1 register
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* Bus access logging configuration register
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*/
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typedef union {
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struct {
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/** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
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* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
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* to enable DMA_2 bus access logging. \\
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* 0: Disable \\
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* 1: Enable\\
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* Bit[7:1]: Reserved
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*/
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uint32_t log_dma_2_ena:8;
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/** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
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* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
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* to enable DMA_3 bus access logging. \\
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* 0: Disable \\
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* 1: Enable\\
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* Bit[7:1]: Reserved
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*/
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uint32_t log_dma_3_ena:8;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} mem_monitor_log_setting1_reg_t;
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/** Type of log_check_data register
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* Configures monitored data in Bus access logging
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*/
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typedef union {
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struct {
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/** log_check_data : R/W; bitpos: [31:0]; default: 0;
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* Configures the data to be monitored during bus accessing.
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*/
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uint32_t log_check_data:32;
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};
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uint32_t val;
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} mem_monitor_log_check_data_reg_t;
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/** Type of log_data_mask register
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* Configures masked data in Bus access logging
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*/
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typedef union {
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struct {
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/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
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* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
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* Configures whether to mask the least significant byte of
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* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
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* 0: Not mask \\
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* 1: Mask\\
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* bit[1]: Configures whether to mask the second least significant byte of
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* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
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* 0: Not mask \\
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* 1: Mask\\
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* bit[2]: Configures whether to mask the second most significant byte of
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* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
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* 0: Not mask \\
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* 1: Mask\\
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* bit[3]: Configures whether to mask the most significant byte of
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* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
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* 0: Not mask \\
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* 1: Mask\\
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*/
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uint32_t log_data_mask:4;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} mem_monitor_log_data_mask_reg_t;
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/** Type of log_min register
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* Configures monitored address space in Bus access logging
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*/
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typedef union {
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struct {
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/** log_min : R/W; bitpos: [31:0]; default: 0;
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* Configures the lower bound address of the monitored address space.
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*/
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uint32_t log_min:32;
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};
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uint32_t val;
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} mem_monitor_log_min_reg_t;
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/** Type of log_max register
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* Configures monitored address space in Bus access logging
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*/
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typedef union {
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struct {
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/** log_max : R/W; bitpos: [31:0]; default: 0;
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* Configures the upper bound address of the monitored address space.
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*/
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uint32_t log_max:32;
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};
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uint32_t val;
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} mem_monitor_log_max_reg_t;
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/** Type of log_mon_addr_update_0 register
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* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
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* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
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*/
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typedef union {
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struct {
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/** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0;
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* Configures the monitored address space of the certain master. Bit[0]: Configures
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* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
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* monitored address space of the HP CPU bus.1: Update\\
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* 0: Not update\\
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* Bit[7:1]: Reserved\\
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*/
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uint32_t log_mon_addr_core_update:8;
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uint32_t reserved_8:23;
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/** log_mon_addr_all_update : WT; bitpos: [31]; default: 0;
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* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
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* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
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* 0: Not update\\
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*/
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uint32_t log_mon_addr_all_update:1;
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};
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uint32_t val;
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} mem_monitor_log_mon_addr_update_0_reg_t;
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/** Type of log_mon_addr_update_1 register
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* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
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* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
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*/
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typedef union {
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struct {
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/** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0;
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* Configures the monitored address space of the certain master. Bit[0]: Configures
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* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
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* monitored address space of the DMA_0 bus.1: Update\\
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* 0: Not update\\
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* Bit[7:1]: Reserved\\
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*/
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uint32_t log_mon_addr_dma_0_update:8;
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/** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0;
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* Configures the monitored address space of the certain master. Bit[0]: Configures
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* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
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* monitored address space of the DMA_1 bus.1: Update\\
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* 0: Not update\\
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* Bit[7:1]: Reserved\\
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*/
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uint32_t log_mon_addr_dma_1_update:8;
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/** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0;
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* Configures the monitored address space of the certain master. Bit[0]: Configures
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* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
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* monitored address space of the DMA_2 bus.1: Update\\
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* 0: Not update\\
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* Bit[7:1]: Reserved\\
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*/
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uint32_t log_mon_addr_dma_2_update:8;
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/** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0;
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* Configures the monitored address space of the certain master. Bit[0]: Configures
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* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
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* monitored address space of the DMA_3 bus.1: Update\\
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* 0: Not update\\
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* Bit[7:1]: Reserved\\
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*/
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uint32_t log_mon_addr_dma_3_update:8;
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};
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uint32_t val;
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} mem_monitor_log_mon_addr_update_1_reg_t;
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/** Type of log_mem_start register
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* Configures the starting address of the storage memory for recorded data
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*/
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typedef union {
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struct {
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/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
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* Configures the starting address of the storage space for recorded data.
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*/
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uint32_t log_mem_start:32;
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};
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uint32_t val;
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} mem_monitor_log_mem_start_reg_t;
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/** Type of log_mem_end register
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* Configures the end address of the storage memory for recorded data
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*/
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typedef union {
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struct {
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/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
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* Configures the ending address of the storage space for recorded data.
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*/
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uint32_t log_mem_end:32;
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};
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uint32_t val;
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} mem_monitor_log_mem_end_reg_t;
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/** Type of log_mem_current_addr register
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* Represents the address for the next write
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*/
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typedef union {
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struct {
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/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
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* Represents the address of the next write.
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*/
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uint32_t log_mem_current_addr:32;
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};
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uint32_t val;
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} mem_monitor_log_mem_current_addr_reg_t;
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/** Type of log_mem_addr_update register
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* Updates the address for the next write with the starting address for the recorded
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* data
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*/
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typedef union {
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struct {
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/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
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* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
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* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
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* 0: Not update (default) \\
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*/
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uint32_t log_mem_addr_update:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} mem_monitor_log_mem_addr_update_reg_t;
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/** Type of log_mem_full_flag register
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* Logging overflow status register
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*/
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typedef union {
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struct {
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/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
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* Represents whether data overflows the storage space.0: Not Overflow\\
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* 1: Overflow\\
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*/
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uint32_t log_mem_full_flag:1;
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/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
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* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
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* clear\\
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* 1: Clear\\
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*/
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uint32_t clr_log_mem_full_flag:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} mem_monitor_log_mem_full_flag_reg_t;
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/** Group: clk register */
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/** Type of clock_gate register
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* Register clock control
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 0;
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* Configures whether to enable the register clock gating.0: Disable\\
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* 1: Enable\\
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} mem_monitor_clock_gate_reg_t;
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/** Group: version register */
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/** Type of date register
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* Version control register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 36733248;
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* Version control register.
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} mem_monitor_date_reg_t;
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typedef struct {
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volatile mem_monitor_log_setting_reg_t log_setting;
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volatile mem_monitor_log_setting1_reg_t log_setting1;
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volatile mem_monitor_log_check_data_reg_t log_check_data;
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volatile mem_monitor_log_data_mask_reg_t log_data_mask;
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volatile mem_monitor_log_min_reg_t log_min;
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volatile mem_monitor_log_max_reg_t log_max;
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volatile mem_monitor_log_mon_addr_update_0_reg_t log_mon_addr_update_0;
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volatile mem_monitor_log_mon_addr_update_1_reg_t log_mon_addr_update_1;
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volatile mem_monitor_log_mem_start_reg_t log_mem_start;
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volatile mem_monitor_log_mem_end_reg_t log_mem_end;
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volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
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volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
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volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
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volatile mem_monitor_clock_gate_reg_t clock_gate;
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uint32_t reserved_038[241];
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volatile mem_monitor_date_reg_t date;
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} mem_monitor_dev_t;
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extern mem_monitor_dev_t TCM_MEM_MONITOR;
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#ifndef __cplusplus
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_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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