mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
b8c6c5334f
On ESP32S3, the default I2C pins of the examples are already used by USB. This commit changes the default pins.
781 lines
22 KiB
C
781 lines
22 KiB
C
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configure Registers */
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/** Type of i2c_scl_low register
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* configure low scl period
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*/
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typedef union {
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struct {
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/** i2c_scl_low_period_reg : R/W; bitpos: [19:0]; default: 256;
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* time period that scl =0
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*/
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uint32_t i2c_scl_low_period_reg:20;
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uint32_t reserved_20:12;
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};
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uint32_t val;
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} rtc_i2c_scl_low_reg_t;
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/** Type of i2c_ctrl register
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* configure i2c ctrl
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*/
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typedef union {
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struct {
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/** i2c_sda_force_out : R/W; bitpos: [0]; default: 0;
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* 1=push pull,0=open drain
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*/
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uint32_t i2c_sda_force_out:1;
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/** i2c_scl_force_out : R/W; bitpos: [1]; default: 0;
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* 1=push pull,0=open drain
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*/
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uint32_t i2c_scl_force_out:1;
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/** i2c_ms_mode : R/W; bitpos: [2]; default: 0;
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* 1=master,0=slave
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*/
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uint32_t i2c_ms_mode:1;
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/** i2c_trans_start : R/W; bitpos: [3]; default: 0;
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* force start
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*/
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uint32_t i2c_trans_start:1;
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/** i2c_tx_lsb_first : R/W; bitpos: [4]; default: 0;
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* transit lsb first
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*/
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uint32_t i2c_tx_lsb_first:1;
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/** i2c_rx_lsb_first : R/W; bitpos: [5]; default: 0;
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* receive lsb first
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*/
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uint32_t i2c_rx_lsb_first:1;
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uint32_t reserved_6:23;
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/** i2c_i2c_ctrl_clk_gate_en : R/W; bitpos: [29]; default: 0;
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* configure i2c ctrl clk enable
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*/
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uint32_t i2c_i2c_ctrl_clk_gate_en:1;
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/** i2c_i2c_reset : R/W; bitpos: [30]; default: 0;
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* rtc i2c sw reset
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*/
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uint32_t i2c_i2c_reset:1;
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/** i2c_i2cclk_en : R/W; bitpos: [31]; default: 0;
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* rtc i2c reg clk gating
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*/
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uint32_t i2c_i2cclk_en:1;
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};
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uint32_t val;
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} rtc_i2c_ctrl_reg_t;
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/** Type of i2c_to register
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* configure time out
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*/
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typedef union {
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struct {
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/** i2c_time_out_reg : R/W; bitpos: [19:0]; default: 65536;
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* time out threshold
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*/
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uint32_t i2c_time_out_reg:20;
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uint32_t reserved_20:12;
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};
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uint32_t val;
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} rtc_i2c_to_reg_t;
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/** Type of i2c_slave_addr register
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* configure slave id
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*/
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typedef union {
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struct {
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/** i2c_slave_addr : R/W; bitpos: [14:0]; default: 0;
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* slave address
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*/
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uint32_t i2c_slave_addr:15;
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uint32_t reserved_15:16;
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/** i2c_addr_10bit_en : R/W; bitpos: [31]; default: 0;
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* i2c 10bit mode enable
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*/
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uint32_t i2c_addr_10bit_en:1;
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};
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uint32_t val;
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} rtc_i2c_slave_addr_reg_t;
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/** Type of i2c_scl_high register
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* configure high scl period
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*/
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typedef union {
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struct {
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/** i2c_scl_high_period_reg : R/W; bitpos: [19:0]; default: 256;
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* time period that scl = 1
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*/
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uint32_t i2c_scl_high_period_reg:20;
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uint32_t reserved_20:12;
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};
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uint32_t val;
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} rtc_i2c_scl_high_reg_t;
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/** Type of i2c_sda_duty register
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* configure sda duty
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*/
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typedef union {
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struct {
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/** i2c_sda_duty_num : R/W; bitpos: [19:0]; default: 16;
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* time period for SDA to toggle after SCL goes low
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*/
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uint32_t i2c_sda_duty_num:20;
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uint32_t reserved_20:12;
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};
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uint32_t val;
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} rtc_i2c_sda_duty_reg_t;
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/** Type of i2c_scl_start_period register
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* configure scl start period
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*/
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typedef union {
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struct {
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/** i2c_scl_start_period : R/W; bitpos: [19:0]; default: 8;
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* time period for SCL to toggle after I2C start is triggered
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*/
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uint32_t i2c_scl_start_period:20;
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uint32_t reserved_20:12;
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};
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uint32_t val;
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} rtc_i2c_scl_start_period_reg_t;
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/** Type of i2c_scl_stop_period register
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* configure scl stop period
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*/
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typedef union {
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struct {
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/** i2c_scl_stop_period : R/W; bitpos: [19:0]; default: 8;
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* time period for SCL to stop after I2C end is triggered
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*/
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uint32_t i2c_scl_stop_period:20;
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uint32_t reserved_20:12;
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};
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uint32_t val;
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} rtc_i2c_scl_stop_period_reg_t;
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/** Type of i2c_data register
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* get i2c data status
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*/
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typedef union {
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struct {
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/** i2c_i2c_rdata : RO; bitpos: [7:0]; default: 0;
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* data received
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*/
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uint32_t i2c_i2c_rdata:8;
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/** i2c_slave_tx_data : R/W; bitpos: [15:8]; default: 0;
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* data sent by slave
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*/
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uint32_t i2c_slave_tx_data:8;
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uint32_t reserved_16:15;
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/** i2c_i2c_done : RO; bitpos: [31]; default: 0;
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* i2c done
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*/
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uint32_t i2c_i2c_done:1;
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};
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uint32_t val;
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} rtc_i2c_data_reg_t;
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/** Type of i2c_cmd0 register
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* i2c commond0 register
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*/
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typedef union {
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struct {
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/** i2c_command0 : R/W; bitpos: [13:0]; default: 2307;
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* command0
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*/
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uint32_t i2c_command0:14;
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uint32_t reserved_14:17;
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/** i2c_command0_done : RO; bitpos: [31]; default: 0;
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* command0_done
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*/
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uint32_t i2c_command0_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd0_reg_t;
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/** Type of i2c_cmd1 register
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* i2c commond1 register
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*/
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typedef union {
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struct {
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/** i2c_command1 : R/W; bitpos: [13:0]; default: 6401;
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* command1
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*/
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uint32_t i2c_command1:14;
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uint32_t reserved_14:17;
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/** i2c_command1_done : RO; bitpos: [31]; default: 0;
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* command1_done
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*/
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uint32_t i2c_command1_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd1_reg_t;
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/** Type of i2c_cmd2 register
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* i2c commond2 register
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*/
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typedef union {
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struct {
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/** i2c_command2 : R/W; bitpos: [13:0]; default: 2306;
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* command2
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*/
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uint32_t i2c_command2:14;
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uint32_t reserved_14:17;
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/** i2c_command2_done : RO; bitpos: [31]; default: 0;
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* command2_done
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*/
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uint32_t i2c_command2_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd2_reg_t;
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/** Type of i2c_cmd3 register
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* i2c commond3 register
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*/
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typedef union {
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struct {
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/** i2c_command3 : R/W; bitpos: [13:0]; default: 257;
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* command3
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*/
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uint32_t i2c_command3:14;
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uint32_t reserved_14:17;
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/** i2c_command3_done : RO; bitpos: [31]; default: 0;
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* command3_done
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*/
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uint32_t i2c_command3_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd3_reg_t;
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/** Type of i2c_cmd4 register
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* i2c commond4 register
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*/
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typedef union {
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struct {
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/** i2c_command4 : R/W; bitpos: [13:0]; default: 2305;
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* command4
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*/
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uint32_t i2c_command4:14;
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uint32_t reserved_14:17;
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/** i2c_command4_done : RO; bitpos: [31]; default: 0;
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* command4_done
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*/
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uint32_t i2c_command4_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd4_reg_t;
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/** Type of i2c_cmd5 register
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* i2c commond5_register
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*/
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typedef union {
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struct {
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/** i2c_command5 : R/W; bitpos: [13:0]; default: 5889;
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* command5
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*/
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uint32_t i2c_command5:14;
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uint32_t reserved_14:17;
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/** i2c_command5_done : RO; bitpos: [31]; default: 0;
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* command5_done
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*/
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uint32_t i2c_command5_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd5_reg_t;
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/** Type of i2c_cmd6 register
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* i2c commond6 register
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*/
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typedef union {
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struct {
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/** i2c_command6 : R/W; bitpos: [13:0]; default: 6401;
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* command6
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*/
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uint32_t i2c_command6:14;
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uint32_t reserved_14:17;
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/** i2c_command6_done : RO; bitpos: [31]; default: 0;
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* command6_done
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*/
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uint32_t i2c_command6_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd6_reg_t;
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/** Type of i2c_cmd7 register
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* i2c commond7 register
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*/
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typedef union {
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struct {
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/** i2c_command7 : R/W; bitpos: [13:0]; default: 2308;
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* command7
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*/
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uint32_t i2c_command7:14;
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uint32_t reserved_14:17;
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/** i2c_command7_done : RO; bitpos: [31]; default: 0;
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* command7_done
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*/
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uint32_t i2c_command7_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd7_reg_t;
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/** Type of i2c_cmd8 register
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* i2c commond8 register
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*/
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typedef union {
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struct {
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/** i2c_command8 : R/W; bitpos: [13:0]; default: 6401;
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* command8
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*/
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uint32_t i2c_command8:14;
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uint32_t reserved_14:17;
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/** i2c_command8_done : RO; bitpos: [31]; default: 0;
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* command8_done
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*/
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uint32_t i2c_command8_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd8_reg_t;
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/** Type of i2c_cmd9 register
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* i2c commond9 register
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*/
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typedef union {
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struct {
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/** i2c_command9 : R/W; bitpos: [13:0]; default: 2307;
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* command9
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*/
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uint32_t i2c_command9:14;
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uint32_t reserved_14:17;
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/** i2c_command9_done : RO; bitpos: [31]; default: 0;
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* command9_done
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*/
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uint32_t i2c_command9_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd9_reg_t;
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/** Type of i2c_cmd10 register
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* i2c commond10 register
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*/
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typedef union {
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struct {
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/** i2c_command10 : R/W; bitpos: [13:0]; default: 257;
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* command10
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*/
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uint32_t i2c_command10:14;
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uint32_t reserved_14:17;
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/** i2c_command10_done : RO; bitpos: [31]; default: 0;
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* command10_done
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*/
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uint32_t i2c_command10_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd10_reg_t;
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/** Type of i2c_cmd11 register
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* i2c commond11 register
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*/
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typedef union {
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struct {
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/** i2c_command11 : R/W; bitpos: [13:0]; default: 2305;
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* command11
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*/
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uint32_t i2c_command11:14;
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uint32_t reserved_14:17;
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/** i2c_command11_done : RO; bitpos: [31]; default: 0;
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* command11_done
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*/
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uint32_t i2c_command11_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd11_reg_t;
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/** Type of i2c_cmd12 register
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* i2c commond12 register
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*/
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typedef union {
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struct {
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/** i2c_command12 : R/W; bitpos: [13:0]; default: 5889;
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* command12
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*/
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uint32_t i2c_command12:14;
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uint32_t reserved_14:17;
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/** i2c_command12_done : RO; bitpos: [31]; default: 0;
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* command12_done
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*/
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uint32_t i2c_command12_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd12_reg_t;
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/** Type of i2c_cmd13 register
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* i2c commond13 register
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*/
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typedef union {
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struct {
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/** i2c_command13 : R/W; bitpos: [13:0]; default: 6401;
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* command13
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*/
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uint32_t i2c_command13:14;
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uint32_t reserved_14:17;
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/** i2c_command13_done : RO; bitpos: [31]; default: 0;
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* command13_done
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*/
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uint32_t i2c_command13_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd13_reg_t;
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/** Type of i2c_cmd14 register
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* i2c commond14 register
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*/
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typedef union {
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struct {
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/** i2c_command14 : R/W; bitpos: [13:0]; default: 0;
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* command14
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*/
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uint32_t i2c_command14:14;
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uint32_t reserved_14:17;
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/** i2c_command14_done : RO; bitpos: [31]; default: 0;
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* command14_done
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*/
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uint32_t i2c_command14_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd14_reg_t;
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/** Type of i2c_cmd15 register
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* i2c commond15 register
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*/
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typedef union {
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struct {
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/** i2c_command15 : R/W; bitpos: [13:0]; default: 0;
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* command15
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*/
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uint32_t i2c_command15:14;
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uint32_t reserved_14:17;
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/** i2c_command15_done : RO; bitpos: [31]; default: 0;
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* command15_done
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*/
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uint32_t i2c_command15_done:1;
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};
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uint32_t val;
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} rtc_i2c_cmd15_reg_t;
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/** Group: status register */
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/** Type of i2c_status register
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* get i2c status
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*/
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typedef union {
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struct {
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/** i2c_ack_rec : RO; bitpos: [0]; default: 0;
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* ack response
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*/
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uint32_t i2c_ack_rec:1;
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/** i2c_slave_rw : RO; bitpos: [1]; default: 0;
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* slave read or write
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*/
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uint32_t i2c_slave_rw:1;
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/** i2c_arb_lost : RO; bitpos: [2]; default: 0;
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* arbitration is lost
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*/
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uint32_t i2c_arb_lost:1;
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/** i2c_bus_busy : RO; bitpos: [3]; default: 0;
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* bus is busy
|
|
*/
|
|
uint32_t i2c_bus_busy:1;
|
|
/** i2c_slave_addressed : RO; bitpos: [4]; default: 0;
|
|
* slave reg sub address
|
|
*/
|
|
uint32_t i2c_slave_addressed:1;
|
|
/** i2c_byte_trans : RO; bitpos: [5]; default: 0;
|
|
* One byte transit done
|
|
*/
|
|
uint32_t i2c_byte_trans:1;
|
|
/** i2c_op_cnt : RO; bitpos: [7:6]; default: 0;
|
|
* which operation is working
|
|
*/
|
|
uint32_t i2c_op_cnt:2;
|
|
uint32_t reserved_8:8;
|
|
/** i2c_shift_reg : RO; bitpos: [23:16]; default: 0;
|
|
* shifter content
|
|
*/
|
|
uint32_t i2c_shift_reg:8;
|
|
/** i2c_scl_main_state_last : RO; bitpos: [26:24]; default: 0;
|
|
* i2c last main status
|
|
*/
|
|
uint32_t i2c_scl_main_state_last:3;
|
|
uint32_t reserved_27:1;
|
|
/** i2c_scl_state_last : RO; bitpos: [30:28]; default: 0;
|
|
* scl last status
|
|
*/
|
|
uint32_t i2c_scl_state_last:3;
|
|
uint32_t reserved_31:1;
|
|
};
|
|
uint32_t val;
|
|
} rtc_i2c_status_reg_t;
|
|
|
|
|
|
/** Group: interrupt Register */
|
|
/** Type of i2c_int_clr register
|
|
* interrupt clear register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** i2c_slave_tran_comp_int_clr : WO; bitpos: [0]; default: 0;
|
|
* clear slave transit complete interrupt
|
|
*/
|
|
uint32_t i2c_slave_tran_comp_int_clr:1;
|
|
/** i2c_arbitration_lost_int_clr : WO; bitpos: [1]; default: 0;
|
|
* clear arbitration lost interrupt
|
|
*/
|
|
uint32_t i2c_arbitration_lost_int_clr:1;
|
|
/** i2c_master_tran_comp_int_clr : WO; bitpos: [2]; default: 0;
|
|
* clear master transit complete interrupt
|
|
*/
|
|
uint32_t i2c_master_tran_comp_int_clr:1;
|
|
/** i2c_trans_complete_int_clr : WO; bitpos: [3]; default: 0;
|
|
* clear transit complete interrupt
|
|
*/
|
|
uint32_t i2c_trans_complete_int_clr:1;
|
|
/** i2c_time_out_int_clr : WO; bitpos: [4]; default: 0;
|
|
* clear time out interrupt
|
|
*/
|
|
uint32_t i2c_time_out_int_clr:1;
|
|
/** i2c_ack_err_int_clr : WO; bitpos: [5]; default: 0;
|
|
* clear ack error interrupt
|
|
*/
|
|
uint32_t i2c_ack_err_int_clr:1;
|
|
/** i2c_rx_data_int_clr : WO; bitpos: [6]; default: 0;
|
|
* clear receive data interrupt
|
|
*/
|
|
uint32_t i2c_rx_data_int_clr:1;
|
|
/** i2c_tx_data_int_clr : WO; bitpos: [7]; default: 0;
|
|
* clear transit load data complete interrupt
|
|
*/
|
|
uint32_t i2c_tx_data_int_clr:1;
|
|
/** i2c_detect_start_int_clr : WO; bitpos: [8]; default: 0;
|
|
* clear detect start interrupt
|
|
*/
|
|
uint32_t i2c_detect_start_int_clr:1;
|
|
uint32_t reserved_9:23;
|
|
};
|
|
uint32_t val;
|
|
} rtc_i2c_int_clr_reg_t;
|
|
|
|
/** Type of i2c_int_raw register
|
|
* interrupt raw register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** i2c_slave_tran_comp_int_raw : RO; bitpos: [0]; default: 0;
|
|
* slave transit complete interrupt raw
|
|
*/
|
|
uint32_t i2c_slave_tran_comp_int_raw:1;
|
|
/** i2c_arbitration_lost_int_raw : RO; bitpos: [1]; default: 0;
|
|
* arbitration lost interrupt raw
|
|
*/
|
|
uint32_t i2c_arbitration_lost_int_raw:1;
|
|
/** i2c_master_tran_comp_int_raw : RO; bitpos: [2]; default: 0;
|
|
* master transit complete interrupt raw
|
|
*/
|
|
uint32_t i2c_master_tran_comp_int_raw:1;
|
|
/** i2c_trans_complete_int_raw : RO; bitpos: [3]; default: 0;
|
|
* transit complete interrupt raw
|
|
*/
|
|
uint32_t i2c_trans_complete_int_raw:1;
|
|
/** i2c_time_out_int_raw : RO; bitpos: [4]; default: 0;
|
|
* time out interrupt raw
|
|
*/
|
|
uint32_t i2c_time_out_int_raw:1;
|
|
/** i2c_ack_err_int_raw : RO; bitpos: [5]; default: 0;
|
|
* ack error interrupt raw
|
|
*/
|
|
uint32_t i2c_ack_err_int_raw:1;
|
|
/** i2c_rx_data_int_raw : RO; bitpos: [6]; default: 0;
|
|
* receive data interrupt raw
|
|
*/
|
|
uint32_t i2c_rx_data_int_raw:1;
|
|
/** i2c_tx_data_int_raw : RO; bitpos: [7]; default: 0;
|
|
* transit data interrupt raw
|
|
*/
|
|
uint32_t i2c_tx_data_int_raw:1;
|
|
/** i2c_detect_start_int_raw : RO; bitpos: [8]; default: 0;
|
|
* detect start interrupt raw
|
|
*/
|
|
uint32_t i2c_detect_start_int_raw:1;
|
|
uint32_t reserved_9:23;
|
|
};
|
|
uint32_t val;
|
|
} rtc_i2c_int_raw_reg_t;
|
|
|
|
/** Type of i2c_int_st register
|
|
* interrupt state register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** i2c_slave_tran_comp_int_st : RO; bitpos: [0]; default: 0;
|
|
* slave transit complete interrupt state
|
|
*/
|
|
uint32_t i2c_slave_tran_comp_int_st:1;
|
|
/** i2c_arbitration_lost_int_st : RO; bitpos: [1]; default: 0;
|
|
* arbitration lost interrupt state
|
|
*/
|
|
uint32_t i2c_arbitration_lost_int_st:1;
|
|
/** i2c_master_tran_comp_int_st : RO; bitpos: [2]; default: 0;
|
|
* master transit complete interrupt state
|
|
*/
|
|
uint32_t i2c_master_tran_comp_int_st:1;
|
|
/** i2c_trans_complete_int_st : RO; bitpos: [3]; default: 0;
|
|
* transit complete interrupt state
|
|
*/
|
|
uint32_t i2c_trans_complete_int_st:1;
|
|
/** i2c_time_out_int_st : RO; bitpos: [4]; default: 0;
|
|
* time out interrupt state
|
|
*/
|
|
uint32_t i2c_time_out_int_st:1;
|
|
/** i2c_ack_err_int_st : RO; bitpos: [5]; default: 0;
|
|
* ack error interrupt state
|
|
*/
|
|
uint32_t i2c_ack_err_int_st:1;
|
|
/** i2c_rx_data_int_st : RO; bitpos: [6]; default: 0;
|
|
* receive data interrupt state
|
|
*/
|
|
uint32_t i2c_rx_data_int_st:1;
|
|
/** i2c_tx_data_int_st : RO; bitpos: [7]; default: 0;
|
|
* transit data interrupt state
|
|
*/
|
|
uint32_t i2c_tx_data_int_st:1;
|
|
/** i2c_detect_start_int_st : RO; bitpos: [8]; default: 0;
|
|
* detect start interrupt state
|
|
*/
|
|
uint32_t i2c_detect_start_int_st:1;
|
|
uint32_t reserved_9:23;
|
|
};
|
|
uint32_t val;
|
|
} rtc_i2c_int_st_reg_t;
|
|
|
|
/** Type of i2c_int_ena register
|
|
* interrupt enable register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** i2c_slave_tran_comp_int_ena : R/W; bitpos: [0]; default: 0;
|
|
* enable slave transit complete interrupt
|
|
*/
|
|
uint32_t i2c_slave_tran_comp_int_ena:1;
|
|
/** i2c_arbitration_lost_int_ena : R/W; bitpos: [1]; default: 0;
|
|
* enable arbitration lost interrupt
|
|
*/
|
|
uint32_t i2c_arbitration_lost_int_ena:1;
|
|
/** i2c_master_tran_comp_int_ena : R/W; bitpos: [2]; default: 0;
|
|
* enable master transit complete interrupt
|
|
*/
|
|
uint32_t i2c_master_tran_comp_int_ena:1;
|
|
/** i2c_trans_complete_int_ena : R/W; bitpos: [3]; default: 0;
|
|
* enable transit complete interrupt
|
|
*/
|
|
uint32_t i2c_trans_complete_int_ena:1;
|
|
/** i2c_time_out_int_ena : R/W; bitpos: [4]; default: 0;
|
|
* enable time out interrupt
|
|
*/
|
|
uint32_t i2c_time_out_int_ena:1;
|
|
/** i2c_ack_err_int_ena : R/W; bitpos: [5]; default: 0;
|
|
* enable eack error interrupt
|
|
*/
|
|
uint32_t i2c_ack_err_int_ena:1;
|
|
/** i2c_rx_data_int_ena : R/W; bitpos: [6]; default: 0;
|
|
* enable receive data interrupt
|
|
*/
|
|
uint32_t i2c_rx_data_int_ena:1;
|
|
/** i2c_tx_data_int_ena : R/W; bitpos: [7]; default: 0;
|
|
* enable transit data interrupt
|
|
*/
|
|
uint32_t i2c_tx_data_int_ena:1;
|
|
/** i2c_detect_start_int_ena : R/W; bitpos: [8]; default: 0;
|
|
* enable detect start interrupt
|
|
*/
|
|
uint32_t i2c_detect_start_int_ena:1;
|
|
uint32_t reserved_9:23;
|
|
};
|
|
uint32_t val;
|
|
} rtc_i2c_int_ena_reg_t;
|
|
|
|
|
|
/** Group: version Registers */
|
|
/** Type of i2c_date register
|
|
* version register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** i2c_i2c_date : R/W; bitpos: [27:0]; default: 26235664;
|
|
* version
|
|
*/
|
|
uint32_t i2c_i2c_date:28;
|
|
uint32_t reserved_28:4;
|
|
};
|
|
uint32_t val;
|
|
} rtc_i2c_date_reg_t;
|
|
|
|
|
|
typedef struct {
|
|
volatile rtc_i2c_scl_low_reg_t i2c_scl_low;
|
|
volatile rtc_i2c_ctrl_reg_t i2c_ctrl;
|
|
volatile rtc_i2c_status_reg_t i2c_status;
|
|
volatile rtc_i2c_to_reg_t i2c_to;
|
|
volatile rtc_i2c_slave_addr_reg_t i2c_slave_addr;
|
|
volatile rtc_i2c_scl_high_reg_t i2c_scl_high;
|
|
volatile rtc_i2c_sda_duty_reg_t i2c_sda_duty;
|
|
volatile rtc_i2c_scl_start_period_reg_t i2c_scl_start_period;
|
|
volatile rtc_i2c_scl_stop_period_reg_t i2c_scl_stop_period;
|
|
volatile rtc_i2c_int_clr_reg_t i2c_int_clr;
|
|
volatile rtc_i2c_int_raw_reg_t i2c_int_raw;
|
|
volatile rtc_i2c_int_st_reg_t i2c_int_st;
|
|
volatile rtc_i2c_int_ena_reg_t i2c_int_ena;
|
|
volatile rtc_i2c_data_reg_t i2c_data;
|
|
volatile rtc_i2c_cmd0_reg_t i2c_cmd0;
|
|
volatile rtc_i2c_cmd1_reg_t i2c_cmd1;
|
|
volatile rtc_i2c_cmd2_reg_t i2c_cmd2;
|
|
volatile rtc_i2c_cmd3_reg_t i2c_cmd3;
|
|
volatile rtc_i2c_cmd4_reg_t i2c_cmd4;
|
|
volatile rtc_i2c_cmd5_reg_t i2c_cmd5;
|
|
volatile rtc_i2c_cmd6_reg_t i2c_cmd6;
|
|
volatile rtc_i2c_cmd7_reg_t i2c_cmd7;
|
|
volatile rtc_i2c_cmd8_reg_t i2c_cmd8;
|
|
volatile rtc_i2c_cmd9_reg_t i2c_cmd9;
|
|
volatile rtc_i2c_cmd10_reg_t i2c_cmd10;
|
|
volatile rtc_i2c_cmd11_reg_t i2c_cmd11;
|
|
volatile rtc_i2c_cmd12_reg_t i2c_cmd12;
|
|
volatile rtc_i2c_cmd13_reg_t i2c_cmd13;
|
|
volatile rtc_i2c_cmd14_reg_t i2c_cmd14;
|
|
volatile rtc_i2c_cmd15_reg_t i2c_cmd15;
|
|
uint32_t reserved_078[33];
|
|
volatile rtc_i2c_date_reg_t i2c_date;
|
|
} rtc_dev_t;
|
|
|
|
|
|
#ifndef __cplusplus
|
|
_Static_assert(sizeof(rtc_dev_t) == 0x100, "Invalid size of rtc_dev_t structure");
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|