mirror of
https://github.com/espressif/esp-idf.git
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138 lines
6.2 KiB
C
138 lines
6.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <string.h>
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#include <stdarg.h>
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "esp_check.h"
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#include "esp_regdma.h"
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#include "esp_private/startup_internal.h"
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#include "esp_private/sleep_retention.h"
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#include "esp_private/sleep_clock.h"
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#include "soc/pcr_reg.h"
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#include "modem/modem_syscon_reg.h"
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#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
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#include "modem/modem_lpcon_reg.h"
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#endif
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static __attribute__((unused)) const char *TAG = "sleep_clock";
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static esp_err_t sleep_clock_system_retention_init(void *arg)
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{
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#if CONFIG_IDF_TARGET_ESP32C6
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#define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
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#elif CONFIG_IDF_TARGET_ESP32H2
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#define N_REGS_PCR() (((PCR_PWDET_SAR_CLK_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
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#endif
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const static sleep_retention_entries_config_t pcr_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* pcr */
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};
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esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_0, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
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ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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}
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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static esp_err_t sleep_clock_modem_retention_init(void *arg)
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{
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#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
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#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
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#define N_REGS_LPCON() (((MODEM_LPCON_MEM_CONF_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1)
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#endif
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#if SOC_WIFI_SUPPORTED
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#define MODEM_WIFI_RETENTION_CLOCK (MODEM_SYSCON_CLK_WIFI_APB_FO | MODEM_SYSCON_CLK_FE_APB_FO)
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#define MODEM_WIFI_RETENTION_CLOCK_MASK (MODEM_SYSCON_CLK_WIFI_APB_FO_M | MODEM_SYSCON_CLK_FE_APB_FO_M)
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#endif
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const static sleep_retention_entries_config_t modem_regs_retention[] = {
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{ .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
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#if SOC_WIFI_SUPPORTED
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{ .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG, MODEM_WIFI_RETENTION_CLOCK, MODEM_WIFI_RETENTION_CLOCK_MASK, 0, 0), .owner = ENTRY(0) }, /* WiFi (MAC, BB and FE) retention clock enable */
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#endif
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#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
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{ .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) } /* MODEM LPCON */
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#endif
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};
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#if SOC_WIFI_SUPPORTED
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const static sleep_retention_entries_config_t modem_retention_clock[] = {
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[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0xf0), MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG, 0x0, MODEM_WIFI_RETENTION_CLOCK_MASK, 0, 0), .owner = ENTRY(0) } /* WiFi (MAC, BB and FE) retention clock disable */
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};
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#endif
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esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_1, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 2 level priority");
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#if SOC_WIFI_SUPPORTED
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err = sleep_retention_entries_create(modem_retention_clock, ARRAY_SIZE(modem_retention_clock), REGDMA_LINK_PRI_7, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, lowest level priority");
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#endif
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ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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}
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#endif
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bool IRAM_ATTR clock_domain_pd_allowed(void)
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{
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const uint32_t inited_modules = sleep_retention_get_inited_modules();
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const uint32_t created_modules = sleep_retention_get_created_modules();
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const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
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/* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
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* through MODEM_SYSCON, when one or more MODEMs are initialized, it is
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* necessary to check the state of CLOCK_MODEM to determine MODEM domain on
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* or off. The clock and reset of digital peripherals are managed through
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* PCR, with TOP domain similar to MODEM domain. */
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uint32_t modem_clk_dep_modules = 0;
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#if SOC_WIFI_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
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#endif
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#if SOC_BT_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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#if SOC_IEEE802154_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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uint32_t mask = 0;
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if (inited_modules & sys_clk_dep_modules) {
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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}
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if (inited_modules & modem_clk_dep_modules) {
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#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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#endif
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}
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return ((inited_modules & mask) == (created_modules & mask));
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}
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ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, BIT(0), 106)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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init_param = (sleep_retention_module_init_param_t) {
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.cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
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#endif
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return ESP_OK;
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}
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