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36 lines
1003 B
C
36 lines
1003 B
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/**
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* The interrupt bit in `mcause` register is always bit 31 regardless of the interrupt controller used
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*/
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#define VECTORS_MCAUSE_INTBIT_MASK (0x80000000)
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#if SOC_INT_CLIC_SUPPORTED
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/* When using the CLIC as their interrupt controller, the `mcause` register contains more information than
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* the interrupt bit and cause:
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* MINHV[30]: CPU is fetching vector interrupt entry address or not
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* MPP[29:28]: MSTATUS.MPP[1:0]
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* MPIL[23:16]: interrupt level before entering interrupt ISR
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*
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* Define the mask that will only keep the cause.
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*/
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#define VECTORS_MCAUSE_REASON_MASK (0x00000fff)
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#else // !if SOC_INT_CLIC_SUPPORTED
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/**
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* For targets that use the former INTC or CLINT/PLIC, the `mcause` shouldn't contain any more information
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* but let's be safe and keep the 32 possible cause values.
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*/
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#define VECTORS_MCAUSE_REASON_MASK (0x0000001f)
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#endif
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