Omar Chebib 78a94dbb6c freertos: Fix delay between interrupt request and trigger on RISC-V ... NOP instructions have been added in order to prevent the code from executing code it shouldn't execute. This is due to a delay between the moment an interrupt is requested and the moment it is fired. It only happens on RISC-V SoC.		2021-02-25 06:57:59 +00:00
..
include/freertos	freertos: add API for getting tick rate on C3	2021-02-23 12:05:52 +08:00
port.c	freertos: Fix delay between interrupt request and trigger on RISC-V	2021-02-25 06:57:59 +00:00
portasm.S	core: fix cases where riscv SP were not 16 byte aligned	2021-02-19 11:26:21 +08:00