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https://github.com/espressif/esp-idf.git
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4f227a4ce3
esp32: Allow SPIRAM_MALLOC_RESERVE_INTERNAL to span multiple regions of memory See merge request idf/esp-idf!2891
259 lines
8.7 KiB
C
259 lines
8.7 KiB
C
/*
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Abstraction layer for spi-ram. For now, it's no more than a stub for the spiram_psram functions, but if
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we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
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*/
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <string.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_spiram.h"
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#include "spiram_psram.h"
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "soc/soc.h"
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#include "esp_heap_caps_init.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/dport_reg.h"
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#include "rom/cache.h"
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#if CONFIG_FREERTOS_UNICORE
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#else
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#if CONFIG_MEMMAP_SPIRAM_CACHE_EVENODD
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#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
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#else
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#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
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#endif
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#endif
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#if CONFIG_SPIRAM_SUPPORT
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static const char* TAG = "spiram";
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#if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
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#define PSRAM_SPEED PSRAM_CACHE_F40M_S40M
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#elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define PSRAM_SPEED PSRAM_CACHE_F80M_S40M
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#elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define PSRAM_SPEED PSRAM_CACHE_F80M_S80M
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#else
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#error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
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#endif
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static bool spiram_inited=false;
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/*
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Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
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true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
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initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
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*/
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bool esp_spiram_test()
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{
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volatile int *spiram=(volatile int*)SOC_EXTRAM_DATA_LOW;
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size_t p;
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size_t s=CONFIG_SPIRAM_SIZE;
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int errct=0;
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int initial_err=-1;
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for (p=0; p<(s/sizeof(int)); p+=8) {
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spiram[p]=p^0xAAAAAAAA;
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}
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for (p=0; p<(s/sizeof(int)); p+=8) {
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if (spiram[p]!=(p^0xAAAAAAAA)) {
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errct++;
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if (errct==1) initial_err=p*4;
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}
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}
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if (errct) {
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ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+SOC_EXTRAM_DATA_LOW);
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return false;
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} else {
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ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
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return true;
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}
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}
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void IRAM_ATTR esp_spiram_init_cache()
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{
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//Enable external RAM in MMU
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cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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//Flush and enable icache for APP CPU
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#if !CONFIG_FREERTOS_UNICORE
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
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cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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#endif
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}
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esp_spiram_volt_t esp_spiram_get_chip_volt()
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{
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if (!spiram_inited) {
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ESP_LOGE(TAG, "SPI RAM not initialized");
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return ESP_SPIRAM_VOLT_INVALID;
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}
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psram_volt_t volt = psram_get_volt();
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switch (volt) {
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case PSRAM_VOLT_1V8:
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return ESP_SPIRAM_VOLT_1V8;
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case PSRAM_VOLT_3V3:
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return ESP_SPIRAM_VOLT_3V3;
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default:
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return ESP_SPIRAM_VOLT_INVALID;
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}
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}
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esp_spiram_size_t esp_spiram_get_chip_size()
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{
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if (!spiram_inited) {
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ESP_LOGE(TAG, "SPI RAM not initialized");
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return ESP_SPIRAM_SIZE_INVALID;
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}
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psram_size_t psram_size = psram_get_size();
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switch (psram_size) {
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case PSRAM_SIZE_32MBITS:
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return ESP_SPIRAM_SIZE_32MBITS;
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case PSRAM_SIZE_64MBITS:
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return ESP_SPIRAM_SIZE_64MBITS;
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default:
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return ESP_SPIRAM_SIZE_INVALID;
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}
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}
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esp_err_t esp_spiram_init()
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{
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esp_err_t r;
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r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
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if (r != ESP_OK) {
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#if CONFIG_SPIRAM_IGNORE_NOTFOUND
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ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out.");
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#endif
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return r;
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}
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ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_F40M_S40M ? "flash 40m sram 40m" : \
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PSRAM_SPEED == PSRAM_CACHE_F80M_S40M ? "flash 80m sram 40m" : \
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PSRAM_SPEED == PSRAM_CACHE_F80M_S80M ? "flash 80m sram 80m" : "ERROR");
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ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
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(PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \
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(PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \
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(PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR");
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spiram_inited=true;
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return ESP_OK;
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}
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esp_err_t esp_spiram_add_to_heapalloc()
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{
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ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", CONFIG_SPIRAM_SIZE/1024);
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//Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
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//no need to explicitly specify them.
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return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_LOW, (intptr_t)SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE-1);
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}
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static uint8_t *dma_heap;
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esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
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ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024);
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/* Pool may be allocated in multiple non-contiguous chunks, depending on available RAM */
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while (size > 0) {
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size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
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next_size = MIN(next_size, size);
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ESP_EARLY_LOGD(TAG, "Allocating block of size %d bytes", next_size);
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dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
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if (!dma_heap || next_size == 0) {
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return ESP_ERR_NO_MEM;
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}
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uint32_t caps[] = { MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT };
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esp_err_t e = heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+next_size-1);
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if (e != ESP_OK) {
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return e;
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}
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size -= next_size;
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}
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return ESP_OK;
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}
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size_t esp_spiram_get_size()
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{
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return CONFIG_SPIRAM_SIZE;
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}
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/*
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Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
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otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
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*/
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void IRAM_ATTR esp_spiram_writeback_cache()
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{
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int x;
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volatile int i=0;
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volatile uint8_t *psram=(volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
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int cache_was_disabled=0;
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if (!spiram_inited) return;
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//We need cache enabled for this to work. Re-enable it if needed; make sure we
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//disable it again on exit as well.
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if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) {
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cache_was_disabled|=(1<<0);
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) {
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cache_was_disabled|=(1<<1);
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
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}
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#endif
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#if CONFIG_FREERTOS_UNICORE
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for (x=0; x<1024*64; x+=32) {
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i+=psram[x];
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}
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#else
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/*
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Note: this assumes the amount of external RAM is >2M. If it is 2M or less, what this code does is undefined. If
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we ever support external RAM chips of 2M or smaller, this may need adjusting.
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*/
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for (x=0; x<1024*64; x+=32) {
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i+=psram[x];
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i+=psram[x+(1024*1024*2)+(1024*64)]; //address picked to also clear cache of app cpu in low/high mode
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}
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#endif
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if (cache_was_disabled&(1<<0)) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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if (cache_was_disabled&(1<<1)) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
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}
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#endif
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}
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#endif
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