mirror of
https://github.com/espressif/esp-idf.git
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333553caf2
fix(hal/include): fix header violations in hal component fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Add comment for a far away `#endif` fix(hal/include): change scope for cpp guard ci: Remove components/hal/ comment from public headers check exceptions Add missing include macro sdkconfig.h for header files Add missing include macro stdbool.h for header files Add missing include macro stdint.h for header files Add missing capability guard macro for header files Add missing cpp guard macro for header files Remove some useless include macros Add some missing `inline` attribute for functions defined in header files Remove components/hal/ from public headers check exceptions fix(hal/include): fix invalid licenses fix(hal/include): fix invalid licenses fix(hal/include): add missing soc_caps.h fix(hal): include soc_caps.h before cap macro is used fix(hal): Remove unnecessary target check fix(hal): fix header and macro problems Add missing include macro Remove loop dependency in hal Add comment for far-away endif fix(hal): Add missing soc_caps.h ci: update check_copyright_ignore.txt Change the sequence of `#include` macro, cpp guard macro Change the wrap scope of capacity macro fix(hal): Change position of C++ guard to pass test
159 lines
4.0 KiB
C
159 lines
4.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The ll is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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// The Lowlevel layer for SPI Flash Encryption.
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#include <stdbool.h>
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#include <string.h>
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#include "soc/system_reg.h"
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#include "soc/hwcrypto_reg.h"
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#include "soc/soc.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/// Choose type of chip you want to encrypt manully
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typedef enum
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{
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FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
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PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
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} flash_encrypt_ll_type_t;
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/**
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* Enable the flash encryption function under spi boot mode and download boot mode.
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*/
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static inline void spi_flash_encrypt_ll_enable(void)
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{
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REG_SET_BIT(DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
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DPORT_ENABLE_SPI_MANUAL_ENCRYPT);
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}
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/**
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* Enable the AES accelerator.
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* Also clear reset on digital signature unit, otherwise AES is held in resetop.
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*/
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static inline void spi_flash_encrypt_ll_aes_accelerator_enable(void)
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{
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REG_SET_BIT(DPORT_CPU_PERIP_CLK_EN1_REG, DPORT_CRYPTO_AES_CLK_EN);
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REG_CLR_BIT(DPORT_CPU_PERIP_RST_EN1_REG, DPORT_CRYPTO_AES_RST | DPORT_CRYPTO_DS_RST);
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}
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/*
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* Disable the flash encryption mode.
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*/
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static inline void spi_flash_encrypt_ll_disable(void)
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{
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REG_CLR_BIT(DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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DPORT_ENABLE_SPI_MANUAL_ENCRYPT);
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}
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/**
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* Choose type of chip you want to encrypt manully
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*
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* @param type The type of chip to be encrypted
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*
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* @note The hardware currently support flash encryption.
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*/
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static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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{
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// Our hardware only support flash encryption
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HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
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REG_WRITE(AES_XTS_DESTINATION_REG, type);
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}
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/**
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* Configure the data size of a single encryption.
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*
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* @param block_size Size of the desired block.
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*/
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static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
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{
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// Desired block should not be larger than the block size.
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REG_WRITE(AES_XTS_SIZE_REG, size >> 5);
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}
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/**
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* Save 32-bit piece of plaintext.
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*
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* @param address the address of written flash partition.
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* @param buffer Buffer to store the input data.
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* @param size Buffer size.
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*/
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static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
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{
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uint32_t plaintext_offs = (address % 64);
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memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size);
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}
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/**
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* Copy the flash address to XTS_AES physical address
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*
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* @param flash_addr flash address to write.
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*/
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static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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{
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REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr);
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}
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/**
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* Start flash encryption
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*/
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static inline void spi_flash_encrypt_ll_calculate_start(void)
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{
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REG_WRITE(AES_XTS_TRIGGER_REG, 1);
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}
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/**
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* Wait for flash encryption termination
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*/
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static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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{
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while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
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}
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}
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/**
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* Finish the flash encryption and make encrypted result accessible to SPI.
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*/
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static inline void spi_flash_encrypt_ll_done(void)
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{
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REG_WRITE(AES_XTS_RELEASE_REG, 1);
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while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
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}
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}
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/**
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* Set to destroy encrypted result
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*/
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static inline void spi_flash_encrypt_ll_destroy(void)
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{
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REG_WRITE(AES_XTS_DESTROY_REG, 1);
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}
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/**
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* Check if is qualified to encrypt the buffer
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*
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* @param address the address of written flash partition.
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* @param length Buffer size.
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*/
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static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
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{
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return ((address % length) == 0) ? true : false;
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}
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#ifdef __cplusplus
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}
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#endif
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