mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
382 lines
9.9 KiB
C
382 lines
9.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Configuration Register */
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/** Type of conf register
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* SYSTIMER_CONF.
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*/
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typedef union {
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struct {
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/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
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* systimer clock force on
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*/
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uint32_t systimer_clk_fo: 1;
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uint32_t reserved_1: 21;
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/** target2_work_en : R/W; bitpos: [22]; default: 0;
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* target2 work enable
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*/
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uint32_t target2_work_en: 1;
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/** target1_work_en : R/W; bitpos: [23]; default: 0;
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* target1 work enable
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*/
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uint32_t target1_work_en: 1;
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/** target0_work_en : R/W; bitpos: [24]; default: 0;
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* target0 work enable
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*/
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uint32_t target0_work_en: 1;
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/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
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* If timer unit1 is stalled when core1 stalled
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*/
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uint32_t timer_unit1_core1_stall_en: 1;
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/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
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* If timer unit1 is stalled when core0 stalled
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*/
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uint32_t timer_unit1_core0_stall_en: 1;
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/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
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* If timer unit0 is stalled when core1 stalled
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*/
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uint32_t timer_unit0_core1_stall_en: 1;
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/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
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* If timer unit0 is stalled when core0 stalled
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*/
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uint32_t timer_unit0_core0_stall_en: 1;
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/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
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* timer unit1 work enable
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*/
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uint32_t timer_unit1_work_en: 1;
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/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
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* timer unit0 work enable
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*/
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uint32_t timer_unit0_work_en: 1;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* register file clk gating
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*/
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uint32_t clk_en: 1;
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};
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uint32_t val;
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} systimer_conf_reg_t;
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/** Type of unit_op register
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* SYSTIMER_UNIT_OP.
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*/
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typedef union {
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struct {
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uint32_t reserved_0: 29;
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/** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
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* reg_timer_unit0_value_valid
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*/
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uint32_t timer_unit_value_valid: 1;
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/** timer_unit_update : WT; bitpos: [30]; default: 0;
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* update timer_unit0
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*/
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uint32_t timer_unit_update: 1;
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uint32_t reserved_32: 1;
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};
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uint32_t val;
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} systimer_unit_op_reg_t;
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/** Type of unit_load register
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* SYSTIMER_UNIT_LOAD
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*/
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typedef struct {
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union {
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struct {
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/** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
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* timer unit load high 32 bit
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*/
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uint32_t timer_unit_load_hi: 20;
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uint32_t reserved_20: 12;
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};
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uint32_t val;
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} hi;
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union {
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struct {
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/** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
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* timer unit load low 32 bit
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*/
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uint32_t timer_unit_load_lo: 32;
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};
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uint32_t val;
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} lo;
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} systimer_unit_load_val_reg_t;
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/** Type of target register
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* SYSTIMER_TARGET.
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*/
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typedef struct {
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union {
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struct {
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/** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
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* timer target high 32 bit
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*/
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uint32_t timer_target_hi: 20;
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uint32_t reserved_20: 12;
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};
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uint32_t val;
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} hi;
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union {
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struct {
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/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
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* timer target low 32 bit
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*/
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uint32_t timer_target_lo: 32;
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};
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uint32_t val;
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} lo;
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} systimer_target_val_reg_t;
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/** Type of target_conf register
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* SYSTIMER_TARGET_CONF.
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*/
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typedef union {
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struct {
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/** target_period : R/W; bitpos: [25:0]; default: 0;
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* target period
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*/
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uint32_t target_period: 26;
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uint32_t reserved_26: 4;
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/** target_period_mode : R/W; bitpos: [30]; default: 0;
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* Set target to period mode
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*/
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uint32_t target_period_mode: 1;
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/** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
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* select which unit to compare
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*/
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uint32_t target_timer_unit_sel: 1;
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};
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uint32_t val;
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} systimer_target_conf_reg_t;
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/** Type of unit_value_hi register
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* SYSTIMER_UNIT_VALUE_HI.
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*/
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typedef struct {
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union {
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struct {
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/** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
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* timer read value high 20bit
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*/
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uint32_t timer_unit_value_hi: 20;
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uint32_t reserved_20: 12;
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};
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uint32_t val;
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} hi;
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union {
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struct {
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/** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
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* timer read value low 32bit
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*/
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uint32_t timer_unit_value_lo: 32;
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};
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uint32_t val;
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} lo;
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} systimer_unit_value_reg_t;
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/** Type of comp_load register
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* SYSTIMER_COMP_LOAD.
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*/
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typedef union {
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struct {
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/** timer_comp_load : WT; bitpos: [0]; default: 0;
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* timer comp load value
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*/
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uint32_t timer_comp_load: 1;
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uint32_t reserved_1: 31;
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};
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uint32_t val;
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} systimer_comp_load_reg_t;
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/** Type of unit_load register
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* SYSTIMER_UNIT_LOAD.
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*/
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typedef union {
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struct {
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/** timer_unit_load : WT; bitpos: [0]; default: 0;
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* timer unit load value
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*/
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uint32_t timer_unit_load: 1;
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uint32_t reserved_1: 31;
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};
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uint32_t val;
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} systimer_unit_load_reg_t;
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/** Interrupt Register */
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/** Type of int_ena register
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* SYSTIMER_INT_ENA.
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*/
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typedef union {
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struct {
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/** target0_int_ena : R/W; bitpos: [0]; default: 0;
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* interupt0 enable
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*/
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uint32_t target0_int_ena: 1;
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/** target1_int_ena : R/W; bitpos: [1]; default: 0;
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* interupt1 enable
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*/
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uint32_t target1_int_ena: 1;
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/** target2_int_ena : R/W; bitpos: [2]; default: 0;
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* interupt2 enable
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*/
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uint32_t target2_int_ena: 1;
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uint32_t reserved_3: 29;
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};
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uint32_t val;
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} systimer_int_ena_reg_t;
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/** Type of int_raw register
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* SYSTIMER_INT_RAW.
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*/
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typedef union {
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struct {
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/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
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* interupt0 raw
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*/
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uint32_t target0_int_raw: 1;
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/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
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* interupt1 raw
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*/
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uint32_t target1_int_raw: 1;
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/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
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* interupt2 raw
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*/
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uint32_t target2_int_raw: 1;
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uint32_t reserved_3: 29;
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};
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uint32_t val;
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} systimer_int_raw_reg_t;
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/** Type of int_clr register
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* SYSTIMER_INT_CLR.
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*/
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typedef union {
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struct {
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/** target0_int_clr : WT; bitpos: [0]; default: 0;
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* interupt0 clear
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*/
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uint32_t target0_int_clr: 1;
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/** target1_int_clr : WT; bitpos: [1]; default: 0;
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* interupt1 clear
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*/
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uint32_t target1_int_clr: 1;
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/** target2_int_clr : WT; bitpos: [2]; default: 0;
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* interupt2 clear
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*/
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uint32_t target2_int_clr: 1;
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uint32_t reserved_3: 29;
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};
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uint32_t val;
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} systimer_int_clr_reg_t;
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/** Type of int_st register
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* SYSTIMER_INT_ST.
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*/
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typedef union {
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struct {
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/** target0_int_st : RO; bitpos: [0]; default: 0;
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* reg_target0_int_st
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*/
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uint32_t target0_int_st: 1;
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/** target1_int_st : RO; bitpos: [1]; default: 0;
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* reg_target1_int_st
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*/
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uint32_t target1_int_st: 1;
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/** target2_int_st : RO; bitpos: [2]; default: 0;
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* reg_target2_int_st
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*/
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uint32_t target2_int_st: 1;
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uint32_t reserved_3: 29;
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};
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uint32_t val;
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} systimer_int_st_reg_t;
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/** Version Register */
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/** Type of date register
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* SYSTIMER_DATE.
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [31:0]; default: 33579377;
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* reg_date
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*/
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uint32_t date: 32;
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};
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uint32_t val;
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} systimer_date_reg_t;
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typedef struct {
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volatile systimer_conf_reg_t conf;
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volatile systimer_unit_op_reg_t unit_op[2];
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volatile systimer_unit_load_val_reg_t unit_load_val[2];
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volatile systimer_target_val_reg_t target_val[3];
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volatile systimer_target_conf_reg_t target_conf[3];
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volatile systimer_unit_value_reg_t unit_val[2];
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volatile systimer_comp_load_reg_t comp_load[3];
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volatile systimer_unit_load_reg_t unit_load[2];
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volatile systimer_int_ena_reg_t int_ena;
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volatile systimer_int_raw_reg_t int_raw;
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volatile systimer_int_clr_reg_t int_clr;
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volatile systimer_int_st_reg_t int_st;
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uint32_t reserved_074;
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uint32_t reserved_078;
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uint32_t reserved_07c;
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uint32_t reserved_080;
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uint32_t reserved_084;
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uint32_t reserved_088;
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uint32_t reserved_08c;
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uint32_t reserved_090;
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uint32_t reserved_094;
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uint32_t reserved_098;
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uint32_t reserved_09c;
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uint32_t reserved_0a0;
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uint32_t reserved_0a4;
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uint32_t reserved_0a8;
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uint32_t reserved_0ac;
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uint32_t reserved_0b0;
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uint32_t reserved_0b4;
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uint32_t reserved_0b8;
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uint32_t reserved_0bc;
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uint32_t reserved_0c0;
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uint32_t reserved_0c4;
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uint32_t reserved_0c8;
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uint32_t reserved_0cc;
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uint32_t reserved_0d0;
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uint32_t reserved_0d4;
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uint32_t reserved_0d8;
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uint32_t reserved_0dc;
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uint32_t reserved_0e0;
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uint32_t reserved_0e4;
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uint32_t reserved_0e8;
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uint32_t reserved_0ec;
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uint32_t reserved_0f0;
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uint32_t reserved_0f4;
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uint32_t reserved_0f8;
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volatile systimer_date_reg_t date;
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} systimer_dev_t;
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extern systimer_dev_t SYSTIMER;
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#ifdef __cplusplus
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}
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#endif
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