mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
366 lines
12 KiB
C
366 lines
12 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_UHCI_STRUCT_H_
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#define _SOC_UHCI_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct uhci_dev_s {
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union {
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struct {
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uint32_t in_rst: 1;
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uint32_t out_rst: 1;
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uint32_t ahbm_fifo_rst: 1;
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uint32_t ahbm_rst: 1;
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uint32_t in_loop_test: 1;
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uint32_t out_loop_test: 1;
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uint32_t out_auto_wrback: 1;
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uint32_t out_no_restart_clr: 1;
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uint32_t out_eof_mode: 1;
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uint32_t uart0_ce: 1;
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uint32_t uart1_ce: 1;
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uint32_t reserved11: 1;
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uint32_t outdscr_burst_en: 1;
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uint32_t indscr_burst_en: 1;
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uint32_t out_data_burst_en: 1;
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uint32_t mem_trans_en: 1;
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uint32_t seper_en: 1;
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uint32_t head_en: 1;
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uint32_t crc_rec_en: 1;
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uint32_t uart_idle_eof_en: 1;
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uint32_t len_eof_en: 1;
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uint32_t encode_crc_en: 1;
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uint32_t clk_en: 1;
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uint32_t uart_rx_brk_eof_en: 1;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t rx_start: 1;
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uint32_t tx_start: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t outlink_eof_err: 1;
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uint32_t out_total_eof: 1;
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uint32_t send_s_q: 1;
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uint32_t send_a_q: 1;
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rx_start: 1;
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uint32_t tx_start: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t outlink_eof_err: 1;
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uint32_t out_total_eof: 1;
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uint32_t send_s_q: 1;
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uint32_t send_a_q: 1;
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t rx_start: 1;
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uint32_t tx_start: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t outlink_eof_err: 1;
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uint32_t out_total_eof: 1;
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uint32_t send_s_q: 1;
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uint32_t send_a_q: 1;
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t rx_start: 1;
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uint32_t tx_start: 1;
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uint32_t rx_hung: 1;
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uint32_t tx_hung: 1;
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uint32_t in_done: 1;
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uint32_t in_suc_eof: 1;
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uint32_t in_err_eof: 1;
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uint32_t out_done: 1;
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uint32_t out_eof: 1;
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uint32_t in_dscr_err: 1;
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uint32_t out_dscr_err: 1;
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uint32_t in_dscr_empty: 1;
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uint32_t outlink_eof_err: 1;
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uint32_t out_total_eof: 1;
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uint32_t send_s_q: 1;
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uint32_t send_a_q: 1;
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uint32_t dma_in_fifo_full_wm: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t full: 1;
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uint32_t empty: 1;
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uint32_t reserved2: 30;
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};
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uint32_t val;
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} dma_out_status;
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union {
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struct {
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uint32_t fifo_wdata: 9;
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uint32_t reserved9: 7;
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uint32_t fifo_push: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} dma_out_push;
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union {
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struct {
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uint32_t full: 1;
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uint32_t empty: 1;
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uint32_t reserved2: 2;
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uint32_t rx_err_cause: 3;
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uint32_t reserved7: 25;
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};
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uint32_t val;
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} dma_in_status;
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union {
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struct {
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uint32_t fifo_rdata: 12;
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uint32_t reserved12: 4;
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uint32_t fifo_pop: 1;
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uint32_t reserved17: 15;
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};
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uint32_t val;
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} dma_in_pop;
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union {
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struct {
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uint32_t addr: 20;
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uint32_t reserved20: 8;
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uint32_t stop: 1;
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uint32_t start: 1;
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uint32_t restart: 1;
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uint32_t park: 1;
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};
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uint32_t val;
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} dma_out_link;
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union {
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struct {
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uint32_t addr: 20;
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uint32_t auto_ret: 1;
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uint32_t reserved21: 7;
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uint32_t stop: 1;
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uint32_t start: 1;
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uint32_t restart: 1;
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uint32_t park: 1;
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};
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uint32_t val;
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} dma_in_link;
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union {
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struct {
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uint32_t check_sum_en: 1;
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uint32_t check_seq_en: 1;
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uint32_t crc_disable: 1;
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uint32_t save_head: 1;
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uint32_t tx_check_sum_re: 1;
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uint32_t tx_ack_num_re: 1;
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uint32_t check_owner: 1;
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uint32_t wait_sw_start: 1;
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uint32_t sw_start: 1;
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uint32_t dma_in_fifo_full_thrs:12;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} conf1;
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union {
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struct {
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uint32_t dscr_addr: 18;
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uint32_t in_dscr_state: 2;
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uint32_t in_state: 3;
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uint32_t fifo_cnt_debug: 5;
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uint32_t decode_state: 3;
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} state0;
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union {
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struct {
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uint32_t outlink_dscr_addr:18;
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uint32_t out_dscr_state: 2;
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uint32_t out_state: 3;
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uint32_t fifo_cnt: 5;
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uint32_t encode_state: 3;
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} state1;
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uint32_t dma_out_eof_des_addr; /**/
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uint32_t dma_in_suc_eof_des_addr; /**/
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uint32_t dma_in_err_eof_des_addr; /**/
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uint32_t dma_out_eof_bfr_des_addr; /**/
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union {
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struct {
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uint32_t test_mode: 3;
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uint32_t reserved3: 1;
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uint32_t test_addr: 2;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} ahb_test;
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uint32_t dma_in_dscr; /**/
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uint32_t dma_in_dscr_bf0; /**/
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uint32_t dma_in_dscr_bf1; /**/
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uint32_t dma_out_dscr; /**/
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uint32_t dma_out_dscr_bf0; /**/
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uint32_t dma_out_dscr_bf1; /**/
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union {
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struct {
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uint32_t tx_c0_esc_en: 1;
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uint32_t tx_db_esc_en: 1;
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uint32_t tx_11_esc_en: 1;
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uint32_t tx_13_esc_en: 1;
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uint32_t rx_c0_esc_en: 1;
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uint32_t rx_db_esc_en: 1;
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uint32_t rx_11_esc_en: 1;
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uint32_t rx_13_esc_en: 1;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} escape_conf;
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union {
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struct {
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uint32_t txfifo_timeout: 8;
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uint32_t txfifo_timeout_shift: 3;
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uint32_t txfifo_timeout_ena: 1;
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uint32_t rxfifo_timeout: 8;
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uint32_t rxfifo_timeout_shift: 3;
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uint32_t rxfifo_timeout_ena: 1;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} hung_conf;
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uint32_t ack_num; /**/
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uint32_t rx_head; /**/
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union {
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struct {
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uint32_t single_send_num: 3;
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uint32_t single_send_en: 1;
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uint32_t always_send_num: 3;
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uint32_t always_send_en: 1;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} quick_sent;
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struct {
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uint32_t w_data[2]; /**/
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} q_data[7];
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union {
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struct {
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uint32_t seper_char: 8;
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uint32_t seper_esc_char0: 8;
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uint32_t seper_esc_char1: 8;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf0;
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union {
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struct {
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uint32_t seq0: 8;
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uint32_t seq0_char0: 8;
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uint32_t seq0_char1: 8;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf1;
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union {
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struct {
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uint32_t seq1: 8;
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uint32_t seq1_char0: 8;
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uint32_t seq1_char1: 8;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf2;
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union {
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struct {
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uint32_t seq2: 8;
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uint32_t seq2_char0: 8;
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uint32_t seq2_char1: 8;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} esc_conf3;
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union {
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struct {
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uint32_t thrs: 13;
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uint32_t reserved13:19;
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};
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uint32_t val;
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} pkt_thres;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t date; /**/
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} uhci_dev_t;
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extern uhci_dev_t UHCI0;
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extern uhci_dev_t UHCI1;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_UHCI_STRUCT_H_ */
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