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https://github.com/espressif/esp-idf.git
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b2c074bb70
When porting an RTOS to the Xtensa architecture, there are a few files that
are common to all Xtensa RTOS ports. These files form the Xtensa RTOS porting
layer (e.g., "xtensa_vectors.S", "xtensa_context.S"). An Xtensa RTOS port is
expected to provide an RTOS specific "xtensa_rtos.h" header to interface with
the Xtensa RTOS porting layer.
Previously, the Xtensa RTOS porting layer files were placed in the FreeRTOS
component. This commit does the following:
1. Moves the Xtensa RTOS porting layer files from the `freertos` component to
the `xtensa` component. The following files were moved:
- xtensa_asm_utils.h
- xtensa_context.S
- xtensa_loadstore_handler.S
- xtensa_vectors.S
2. Refactored xtensa component include paths to separate Xtensa RTOS porting
layer headers.
- Xtensa HAL headers included via `#include <xtensa/...h>`
- Xtensa RTOS porting layer headers included via `#include <...h>`
Note: The xtensa files in the Amazon SMP FreeRTOS port are not moved/deleted in
this commit to ensure the moved files retain a clean diff history.
550 lines
14 KiB
ArmAsm
550 lines
14 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* LoadStoreErrorCause: Occurs when trying to access 32 bit addressable memory region as 8 bit or 16 bit
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* LoadStoreAlignmentCause: Occurs when trying to access in an unaligned manner
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*
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* xxxx xxxx = imm8 field
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* yyyy = imm4 field
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* ssss = s field
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* tttt = t field
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*
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* 16 0
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* -------------------
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* L32I.N yyyy ssss tttt 1000
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* S32I.N yyyy ssss tttt 1001
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*
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* 23 0
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* -----------------------------
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* L8UI xxxx xxxx 0000 ssss tttt 0010 <- LoadStoreError
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* L16UI xxxx xxxx 0001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment
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* L16SI xxxx xxxx 1001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment
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* L32I xxxx xxxx 0010 ssss tttt 0010 <- LoadStoreAlignment
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*
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* S8I xxxx xxxx 0100 ssss tttt 0010 <- LoadStoreError
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* S16I xxxx xxxx 0101 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment
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* S32I xxxx xxxx 0110 ssss tttt 0010 <- LoadStoreAlignment
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*
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* ******* UNSUPPORTED *******
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*
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* L32E 0000 1001 rrrr ssss tttt 0000
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* S32E 0100 1001 rrrr ssss tttt 0000
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* -----------------------------
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*/
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#include "xtensa_rtos.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#define LOADSTORE_HANDLER_STACK_SZ 8
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.section .bss, "aw"
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.balign 16
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LoadStoreHandlerStack:
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.rept LOADSTORE_HANDLER_STACK_SZ
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.word 0
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.endr
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/* LoadStoreErrorCause handler:
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*
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* Completes 8-bit or 16-bit load/store instructions from 32-bit aligned memory region
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* Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
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*/
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.global LoadStoreErrorHandler
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.section .iram1, "ax"
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.literal_position
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.balign 4
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LoadStoreErrorHandler:
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.type LoadStoreErrorHandler, @function
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wsr a0, depc // Save return address in depc
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mov a0, sp
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movi sp, LoadStoreHandlerStack
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s32i a0, sp, 0x04 // Since a0 contains value of a1
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s32i a2, sp, 0x08
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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rsr a0, sar // Save SAR in a0 to restore later
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/* Check whether the address lies in the valid range */
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rsr a3, excvaddr
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movi a4, _iram_text_end // End of code section of IRAM
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bge a3, a4, 1f
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movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region
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blt a3, a4, .LS_wrong_opcode
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movi a4, SOC_CACHE_APP_HIGH
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bge a3, a4, .LS_wrong_opcode
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j 2f
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1:
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movi a4, SOC_IRAM_HIGH // End of IRAM address range
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bge a3, a4, .LS_wrong_opcode
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2:
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/* Examine the opcode which generated the exception */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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rsr a2, epc1
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movi a4, ~3
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ssa8l a2 // sar is now correct shift for aligned read
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and a2, a2, a4 // a2 now 4-byte aligned address of instruction
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l32i a4, a2, 0
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l32i a2, a2, 4
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src a2, a2, a4 // a2 now instruction that failed
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bbci a2, 1, .LS_wrong_opcode
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bbsi a2, 14, .LSE_store_op // Store instruction
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/* l8/l16ui/l16si */
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movi a4, ~3
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and a4, a3, a4 // a4 now word aligned read address
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ssa8l a3 // sar is now shift to extract a3's byte
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l32i a4, a4, 0 // perform the actual read
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srl a4, a4 // shift right correct distance
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extui a3, a2, 12, 4
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bnez a3, 1f // l16ui/l16si
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extui a4, a4, 0, 8 // mask off bits needed for an l8
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j 2f
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1:
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extui a4, a4, 0, 16
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bbci a2, 15, 2f // l16ui
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/* Sign adjustment */
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slli a4, a4, 16
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srai a4, a4, 16 // a4 contains the value
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2:
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/* a4 contains the value */
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rsr a3, epc1
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addi a3, a3, 3
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wsr a3, epc1
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wsr a0, sar
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rsr a0, excsave1
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extui a2, a2, 3, 5
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blti a2, 10, .LSE_stack_reg
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movi a3, .LS_jumptable_base
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addx8 a2, a2, a3 // a2 is now the address to jump to
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l32i a3, sp, 0x0c
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jx a2
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.LSE_stack_reg:
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addx2 a2, a2, sp
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s32i a4, a2, 0
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/* Restore all values */
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l32i a4, sp, 0x10
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l32i a3, sp, 0x0c
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rfe
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.LSE_store_op:
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s32i a5, a1, 0x14
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s32i a6, a1, 0x18
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/* a2 -> instruction that caused the error */
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/* a3 -> unaligned address */
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extui a4, a2, 4, 4
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blti a4, 7, 1f
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movi a5, .LSE_store_reg
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addx8 a5, a4, a5
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jx a5
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1:
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addx4 a4, a4, sp
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l32i a4, a4, 0
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.LSE_store_data:
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/* a4 contains the value */
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rsr a6, epc1
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addi a6, a6, 3
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wsr a6, epc1
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ssa8b a3
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movi a5, -1
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bbsi a2, 12, 1f // s16
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extui a4, a4, 0, 8
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movi a6, 0xff
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j 2f
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1:
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extui a4, a4, 0, 16
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movi a6, 0xffff
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2:
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sll a4, a4 // shift the value to proper offset
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sll a6, a6
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xor a5, a5, a6 // a5 contains the mask
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movi a6, ~3
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and a3, a3, a6 // a3 has the aligned address
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l32i a6, a3, 0 // a6 contains the data at the aligned address
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and a6, a6, a5
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or a4, a6, a4
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s32i a4, a3, 0
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/* Restore registers */
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wsr a0, sar
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l32i a6, sp, 0x18
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l32i a5, sp, 0x14
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l32i a4, sp, 0x10
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l32i a3, sp, 0x0c
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rsr a0, excsave1
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rfe
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.LSE_store_reg:
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.org .LSE_store_reg + (7 * 8)
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mov a4, a7
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j .LSE_store_data
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.org .LSE_store_reg + (8 * 8)
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mov a4, a8
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j .LSE_store_data
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.org .LSE_store_reg + (9 * 8)
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mov a4, a9
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j .LSE_store_data
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.org .LSE_store_reg + (10 * 8)
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mov a4, a10
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j .LSE_store_data
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.org .LSE_store_reg + (11 * 8)
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mov a4, a11
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j .LSE_store_data
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.org .LSE_store_reg + (12 * 8)
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mov a4, a12
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j .LSE_store_data
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.org .LSE_store_reg + (13 * 8)
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mov a4, a13
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j .LSE_store_data
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.org .LSE_store_reg + (14 * 8)
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mov a4, a14
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j .LSE_store_data
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.org .LSE_store_reg + (15 * 8)
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mov a4, a15
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j .LSE_store_data
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/* LoadStoreAlignmentCause handler:
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*
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* Completes unaligned 16-bit and 32-bit load/store instructions from 32-bit aligned memory region
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* Called from UserExceptionVector if EXCCAUSE is LoadStoreAlignmentCause
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*/
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.global AlignmentErrorHandler
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.section .iram1, "ax"
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.literal_position
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.balign 4
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AlignmentErrorHandler:
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.type AlignmentErrorHandler, @function
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wsr a0, depc // Save return address in depc
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mov a0, sp
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movi sp, LoadStoreHandlerStack
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s32i a0, sp, 0x04 // Since a0 contains value of a1
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s32i a2, sp, 0x08
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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rsr a0, sar // Save SAR in a0 to restore later
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/* Check whether the address lies in the valid range */
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rsr a3, excvaddr
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movi a4, _iram_text_end // End of code section of IRAM
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bge a3, a4, 1f
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movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region
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blt a3, a4, .LS_wrong_opcode
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movi a4, SOC_CACHE_APP_HIGH
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bge a3, a4, .LS_wrong_opcode
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j 2f
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1:
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movi a4, SOC_IRAM_HIGH // End of IRAM address range
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bge a3, a4, .LS_wrong_opcode
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2:
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/* Examine the opcode which generated the exception */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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rsr a2, epc1
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movi a4, ~3
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ssa8l a2 // sar is now correct shift for aligned read
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and a2, a2, a4 // a2 now 4-byte aligned address of instruction
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l32i a4, a2, 0
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l32i a2, a2, 4
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/* a2 has the instruction that caused the error */
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src a2, a2, a4
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extui a4, a2, 0, 4
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addi a4, a4, -9
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beqz a4, .LSA_store_op
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bbsi a2, 14, .LSA_store_op
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ssa8l a3 // a3 contains the unaligned address
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movi a4, ~3
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and a4, a3, a4 // a4 has the aligned address
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l32i a3, a4, 0
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l32i a4, a4, 4
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src a4, a4, a3
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rsr a3, epc1
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addi a3, a3, 2
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bbsi a2, 3, 1f // l32i.n
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bbci a2, 1, .LS_wrong_opcode
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addi a3, a3, 1
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bbsi a2, 13, 1f // l32
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extui a4, a4, 0, 16
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bbci a2, 15, 1f // l16ui
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/* Sign adjustment */
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slli a4, a4, 16
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srai a4, a4, 16 // a4 contains the value
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1:
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wsr a3, epc1
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wsr a0, sar
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rsr a0, excsave1
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extui a2, a2, 4, 4
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blti a2, 5, .LSA_stack_reg // a3 contains the target register
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movi a3, .LS_jumptable_base
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slli a2, a2, 4
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add a2, a2, a3 // a2 is now the address to jump to
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l32i a3, sp, 0x0c
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jx a2
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.LSA_stack_reg:
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addx4 a2, a2, sp
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s32i a4, a2, 0
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/* Restore all values */
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l32i a4, sp, 0x10
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l32i a3, sp, 0x0c
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rfe
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/* Store instruction */
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.LSA_store_op:
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s32i a5, sp, 0x14
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s32i a6, sp, 0x18
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s32i a7, sp, 0x1c
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/* a2 -> instruction that caused the error */
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/* a3 -> unaligned address */
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extui a4, a2, 4, 4
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blti a4, 8, 1f
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movi a5, .LSA_store_reg
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addx8 a5, a4, a5
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jx a5
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1:
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addx4 a4, a4, sp
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l32i a4, a4, 0 // a4 contains the value
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.LSA_store_data:
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movi a6, 0
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rsr a7, epc1
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addi a7, a7 ,2
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bbsi a2, 3, 1f // s32i.n
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bbci a2, 1, .LS_wrong_opcode
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addi a7, a7, 1
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bbsi a2, 13, 1f // s32i
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movi a5, -1
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extui a4, a4, 0, 16
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slli a6, a5, 16 // 0xffff0000
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1:
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wsr a7, epc1
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movi a5, ~3
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and a5, a3, a5 // a5 has the aligned address
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ssa8b a3
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movi a3, -1
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src a7, a6, a3
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src a3, a3, a6
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/* Store data on lower address */
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l32i a6, a5, 0
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and a6, a6, a7
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sll a7, a4
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or a6, a6, a7
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s32i a6, a5, 0
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/* Store data on higher address */
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l32i a7, a5, 4
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srl a6, a4
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and a3, a7, a3
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or a3, a3, a6
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s32i a3, a5, 4
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/* Restore registers */
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wsr a0, sar
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rsr a0, excsave1
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l32i a7, sp, 0x1c
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l32i a6, sp, 0x18
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l32i a5, sp, 0x14
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l32i a4, sp, 0x10
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l32i a3, sp, 0x0c
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rfe
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.LSA_store_reg:
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.org .LSA_store_reg + (8 * 8)
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mov a4, a8
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j .LSA_store_data
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.org .LSA_store_reg + (9 * 8)
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mov a4, a9
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j .LSA_store_data
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.org .LSA_store_reg + (10 * 8)
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mov a4, a10
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j .LSA_store_data
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.org .LSA_store_reg + (11 * 8)
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mov a4, a11
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j .LSA_store_data
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.org .LSA_store_reg + (12 * 8)
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mov a4, a12
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j .LSA_store_data
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.org .LSA_store_reg + (13 * 8)
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mov a4, a13
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j .LSA_store_data
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.org .LSA_store_reg + (14 * 8)
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mov a4, a14
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j .LSA_store_data
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.org .LSA_store_reg + (15 * 8)
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mov a4, a15
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j .LSA_store_data
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/*
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* Common routines for both the exception handlers
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*/
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.balign 4
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.LS_jumptable:
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/* The first 5 entries (80 bytes) of this table are unused (registers
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a0..a4 are handled separately above). Rather than have a whole bunch
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of wasted space, just pretend that the table starts 80 bytes
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earlier in memory. */
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.set .LS_jumptable_base, .LS_jumptable - (16 * 5)
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.org .LS_jumptable_base + (16 * 5)
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mov a5, a4
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l32i a4, sp, 0x10
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rfe
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.org .LS_jumptable_base + (16 * 6)
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mov a6, a4
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l32i a4, sp, 0x10
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rfe
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.org .LS_jumptable_base + (16 * 7)
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mov a7, a4
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l32i a4, sp, 0x10
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rfe
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.org .LS_jumptable_base + (16 * 8)
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mov a8, a4
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l32i a4, sp, 0x10
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l32i a2, sp, 0x08
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l32i a1, sp, 0x04
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rfe
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.org .LS_jumptable_base + (16 * 9)
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mov a9, a4
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l32i a4, sp, 0x10
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rfe
|
|
|
|
.org .LS_jumptable_base + (16 * 10)
|
|
mov a10, a4
|
|
l32i a4, sp, 0x10
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rfe
|
|
|
|
.org .LS_jumptable_base + (16 * 11)
|
|
mov a11, a4
|
|
l32i a4, sp, 0x10
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rfe
|
|
|
|
.org .LS_jumptable_base + (16 * 12)
|
|
mov a12, a4
|
|
l32i a4, sp, 0x10
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rfe
|
|
|
|
.org .LS_jumptable_base + (16 * 13)
|
|
mov a13, a4
|
|
l32i a4, sp, 0x10
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rfe
|
|
|
|
.org .LS_jumptable_base + (16 * 14)
|
|
mov a14, a4
|
|
l32i a4, sp, 0x10
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rfe
|
|
|
|
.org .LS_jumptable_base + (16 * 15)
|
|
mov a15, a4
|
|
l32i a4, sp, 0x10
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rfe
|
|
|
|
.LS_wrong_opcode:
|
|
/* Reaches here if the address is in invalid range or the opcode isn't supported.
|
|
* Restore registers and jump back to _xt_user_exc
|
|
*/
|
|
wsr a0, sar
|
|
l32i a4, sp, 0x10
|
|
l32i a3, sp, 0x0c
|
|
l32i a2, sp, 0x08
|
|
l32i a1, sp, 0x04
|
|
rsr a0, depc
|
|
ret // Equivalent to jx a0
|