esp-idf/components/ulp/ulp_riscv
Marius Vikhammer cd634f76d4 ulp-riscv: always force COCPU clock on S3
The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU
2022-10-25 13:50:55 +08:00
..
include ulp: fix missing cpp header guard 2022-08-01 10:19:32 +08:00
ulp_core ulp: migrate tests to pytest embedded 2022-08-03 09:36:17 +08:00
ulp_riscv_adc.c esp_adc: move adc common hw related code into esp_hw_support 2022-07-28 03:49:48 +00:00
ulp_riscv.c ulp-riscv: always force COCPU clock on S3 2022-10-25 13:50:55 +08:00