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6e6b9ec5a6
The previously used splits between memory allocated for ROM code,
2nd stage bootloader and the app were somewhat safe and conservative.
This resulted in some space being unavailable for static allocation
in the app.
This commit increases the space available for static allocation to the
maximum possible amount.
1. Some of the ROM code static allocation is only used in UART/USB/SPI
download modes. This region ("shared buffers") has been placed at
the lower end of ROM memory area, to be reusable in flash boot
mode. The 2nd stage bootloader linker script is modified to "pack"
all sections exactly up to the end but with roughly 8K margin between
startup stacks.
2. Instead of calculating the sections placement and hardcoding the
addresses in the LD script again, rewrite it to calculate the
start address of each memory region automatically based on the
logic above.
3. Adjust the app memory layout (SRAM_IRAM_END) accordingly,
increasing the space available for static allocation.
Overall these changes increase the space available for static
allocation by about 78kB.
The downside of these changes is that the 2nd stage bootloader .data
segment is now directly adjacent to the startup stack on the PRO CPU.
Previously, there was effectively about 78kB of extra stack space for
the PRO CPU, before the stack would run into the data segment.
154 lines
5.8 KiB
Plaintext
154 lines
5.8 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* ESP32-S3 Linker Script Memory Layout
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* This file describes the memory layout (memory blocks) by virtual memory addresses.
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* This linker script is passed through the C preprocessor to include configuration options.
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* Please use preprocessor features sparingly!
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* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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#include "ld.common"
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#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
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#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
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#else
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#define ESP_BOOTLOADER_RESERVE_RTC 0
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#endif
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/*
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* 40370000 <- IRAM/Icache -> 40378000 <- D/IRAM (I) -> 403E0000
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* 3FC88000 <- D/IRAM (D) -> 3FCF0000 <- DRAM/DCache -> 3FD00000
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*
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* Startup code uses the IRAM from 0x403BA000 to 0x403E0000, which is not available for static
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* memory, but can only be used after app starts.
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*
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* D cache use the memory from high address, so when it's configured to 16K/32K, the region
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* 0x3FCF000 ~ (3FD00000 - DATA_CACHE_SIZE) should be available. This region is not used as
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* static memory, leaving to the heap.
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*/
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#define SRAM_IRAM_START 0x40370000
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#define SRAM_DIRAM_I_START 0x40378000
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#define SRAM_IRAM_END 0x403CC700 /* Please refer to ESP32-S3 bootloader.ld for more information on this */
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#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
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#define SRAM_DRAM_START 0x3FC88000
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#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) /* 2nd stage bootloader iram_loader_seg start address */
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#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
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#define ICACHE_SIZE 0x8000
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#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define DCACHE_SIZE 0x10000
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#define SRAM_DRAM_ORG (SRAM_DRAM_START)
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#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
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ASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
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#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE
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#else
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#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
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#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
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MEMORY
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{
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/**
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* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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* are connected to the data port of the CPU and eg allow byte-wise access.
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*/
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/* IRAM for PRO CPU. */
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iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped instruction data */
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iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20
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/**
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* (0x20 offset above is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
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/**
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* RTC fast memory (same block as above), viewed from data bus
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*/
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rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
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/**
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* RTC slow memory (data accessible). Persists over deep sleep.
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* Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
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len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
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}
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#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
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/* static data ends at defined address */
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_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;
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#else
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_static_data_end = _bss_end;
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#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000;
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_data_seg_org = ORIGIN(rtc_data_seg);
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#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
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REGION_ALIAS("rtc_data_location", rtc_data_seg );
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#else
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REGION_ALIAS("rtc_data_location", rtc_slow_seg );
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#endif // CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_code_seg", iram0_2_seg);
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#else
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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#else
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
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* also be first in the segment.
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*/
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
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".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
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#endif
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