esp-idf/components/esp_rom/esp32s3/Kconfig.soc_caps.in
gaoxiaojie 4a2f38930b fix(esp32s3): patch Cache_WriteBack_Addr api
Need to ensure that the cacheline being written back will not be
accessed during the write back process.
2023-07-21 11:46:45 +08:00

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#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_HAS_MZ_CRC32
bool
default y
config ESP_ROM_HAS_JPEG_DECODE
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL
bool
default y
config ESP_ROM_HAS_RETARGETABLE_LOCKING
bool
default y
config ESP_ROM_USB_SERIAL_DEVICE_NUM
int
default 4
config ESP_ROM_HAS_ERASE_0_REGION_BUG
bool
default y
config ESP_ROM_GET_CLK_FREQ
bool
default y
config ESP_ROM_HAS_HAL_WDT
bool
default y
config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
bool
default y
config ESP_ROM_HAS_ETS_PRINTF_BUG
bool
default y
config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG
bool
default y
config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
bool
default y
config ESP_ROM_HAS_CACHE_WRITEBACK_BUG
bool
default y