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4a2f38930b
Need to ensure that the cacheline being written back will not be accessed during the write back process.
65 lines
1.0 KiB
Plaintext
65 lines
1.0 KiB
Plaintext
#####################################################
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# This file is auto-generated from SoC caps
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# using gen_soc_caps_kconfig.py, do not edit manually
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#####################################################
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config ESP_ROM_HAS_CRC_LE
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bool
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default y
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config ESP_ROM_HAS_CRC_BE
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bool
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default y
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config ESP_ROM_HAS_MZ_CRC32
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bool
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default y
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config ESP_ROM_HAS_JPEG_DECODE
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bool
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default y
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config ESP_ROM_UART_CLK_IS_XTAL
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bool
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default y
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config ESP_ROM_HAS_RETARGETABLE_LOCKING
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bool
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default y
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config ESP_ROM_USB_SERIAL_DEVICE_NUM
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int
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default 4
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config ESP_ROM_HAS_ERASE_0_REGION_BUG
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bool
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default y
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config ESP_ROM_GET_CLK_FREQ
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bool
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default y
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config ESP_ROM_HAS_HAL_WDT
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bool
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default y
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config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
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bool
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default y
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config ESP_ROM_HAS_ETS_PRINTF_BUG
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bool
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default y
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config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG
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bool
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default y
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config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
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bool
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default y
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config ESP_ROM_HAS_CACHE_WRITEBACK_BUG
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bool
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default y
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