Angus Gratton 32756b165e bootloader: Add fault injection resistance to Secure Boot bootloader verification ... Goal is that multiple faults would be required to bypass a boot-time signature check. - Also strengthens some address range checks for safe app memory addresses - Change pre-enable logic to also check the bootloader signature before enabling SBV2 on ESP32 Add some additional checks for invalid sections: - Sections only partially in DRAM or IRAM are invalid - If a section is in D/IRAM, allow the possibility only some is in D/IRAM - Only pass sections that are entirely in the same type of RTC memory region		2020-03-06 01:16:04 +05:30
..
hal	spi: fix iomux, timing and address phase issues for esp32s2beta	2019-12-23 10:23:00 +08:00
soc	bootloader: Add fault injection resistance to Secure Boot bootloader verification	2020-03-06 01:16:04 +05:30