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81 lines
2.4 KiB
C
81 lines
2.4 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** LP_TEE_M0_MODE_CTRL_REG register
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* TEE mode control register
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*/
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#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
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/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
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* Configures M0 security level mode.\\
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* 0: tee_mode \\
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* 1: ree_mode0 \\
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* 2: ree_mode1 \\
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* 3: ree_mode2 \\
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*/
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#define LP_TEE_M0_MODE 0x00000003U
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#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
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#define LP_TEE_M0_MODE_V 0x00000003U
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#define LP_TEE_M0_MODE_S 0
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/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
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* Set 1 to lock m0 tee configuration
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*/
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#define LP_TEE_M0_LOCK (BIT(2))
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#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S)
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#define LP_TEE_M0_LOCK_V 0x00000001U
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#define LP_TEE_M0_LOCK_S 2
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/** LP_TEE_CLOCK_GATE_REG register
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* Clock gating register
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*/
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#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
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/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
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* Configures whether to keep the clock always on.\\
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* 0: enable automatic clock gating \\
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* 1: keep the clock always on \\
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*/
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#define LP_TEE_CLK_EN (BIT(0))
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#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
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#define LP_TEE_CLK_EN_V 0x00000001U
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#define LP_TEE_CLK_EN_S 0
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/** LP_TEE_FORCE_ACC_HP_REG register
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* Force access to hpmem configuration register
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*/
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#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
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/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
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* Configures whether to allow LP CPU to force access to HP_MEM regardless of
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* permission management.\\
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* 0: disable force access HP_MEM \\
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* 1: enable force access HP_MEM \\
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*/
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#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0))
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#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
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#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U
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#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0
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/** LP_TEE_DATE_REG register
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* Version control register
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*/
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#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
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/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
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* Version control register
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*/
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#define LP_TEE_DATE_REG 0x0FFFFFFFU
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#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
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#define LP_TEE_DATE_REG_V 0x0FFFFFFFU
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#define LP_TEE_DATE_REG_S 0
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#ifdef __cplusplus
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}
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#endif
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