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613 lines
16 KiB
C
613 lines
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "soc/pcr_struct.h"
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#include "soc/parl_io_struct.h"
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#include "hal/parlio_types.h"
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#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
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#define PARLIO_LL_RX_MAX_CLOCK_DIV 0x10000
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#define PARLIO_LL_RX_MAX_TIMEOUT 0xFFFF
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#define PARLIO_LL_TX_MAX_BYTES_PER_FRAME 0xFFFF
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#define PARLIO_LL_TX_MAX_BITS_PER_FRAME (PARLIO_LL_TX_MAX_BYTES_PER_FRAME * 8)
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#define PARLIO_LL_TX_MAX_CLOCK_DIV 0x10000
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#define PARLIO_LL_EVENT_TX_FIFO_EMPTY (1 << 0)
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#define PARLIO_LL_EVENT_RX_FIFO_FULL (1 << 1)
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#define PARLIO_LL_EVENT_TX_EOF (1 << 2)
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#define PARLIO_LL_EVENT_TX_MASK (PARLIO_LL_EVENT_TX_FIFO_EMPTY | PARLIO_LL_EVENT_TX_EOF)
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#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL)
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#define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 15 // TXD[15] can be used a valid signal
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PARLIO_LL_CLK_SRC_XTAL = PARLIO_CLK_SRC_XTAL,
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PARLIO_LL_CLK_SRC_PLL_F240M = PARLIO_CLK_SRC_PLL_F240M,
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PARLIO_LL_CLK_SRC_PAD, // clock source from GPIO pad
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} parlio_ll_clock_source_t;
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typedef enum {
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PARLIO_LL_RX_EOF_COND_RX_FULL, /*!< RX unit generates EOF event when it receives enough data */
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PARLIO_LL_RX_EOF_COND_EN_INACTIVE, /*!< RX unit generates EOF event when the external enable signal becomes inactive */
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} parlio_ll_rx_eof_cond_t;
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///////////////////////////////////////RX Unit///////////////////////////////////////
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/**
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* @brief Set the clock source for the RX unit
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*
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* @param dev Parallel IO register base address
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* @param src Clock source
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*/
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static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_ll_clock_source_t src)
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{
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(void)dev;
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uint32_t clk_sel = 0;
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switch (src) {
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case PARLIO_LL_CLK_SRC_XTAL:
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clk_sel = 0;
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break;
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case PARLIO_LL_CLK_SRC_PLL_F240M:
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clk_sel = 1;
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break;
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case PARLIO_LL_CLK_SRC_PAD:
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clk_sel = 3;
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break;
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default: // unsupported clock source
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HAL_ASSERT(false);
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break;
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}
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PCR.parl_clk_rx_conf.parl_clk_rx_sel = clk_sel;
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}
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/**
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* @brief Set the clock divider for the RX unit
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*
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* @param dev Parallel IO register base address
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* @param div Clock divider
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*/
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static inline void parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, uint32_t div)
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{
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(void)dev;
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HAL_ASSERT(div > 0 && div <= PARLIO_LL_RX_MAX_CLOCK_DIV);
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PCR.parl_clk_rx_conf.parl_clk_rx_div_num = div - 1;
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}
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/**
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* @brief Reset the RX unit Core clock domain
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*
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* @param dev Parallel IO register base address
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_reset_clock(parl_io_dev_t *dev)
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{
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(void)dev;
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PCR.parl_clk_rx_conf.parl_rx_rst_en = 1;
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PCR.parl_clk_rx_conf.parl_rx_rst_en = 0;
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}
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/**
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* @brief Enable the RX unit Core clock domain
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
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{
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(void)dev;
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PCR.parl_clk_rx_conf.parl_clk_rx_en = en;
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}
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/**
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* @brief Set the condition to generate the RX EOF event
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*
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* @param dev Parallel IO register base address
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* @param cond RX EOF condition
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*/
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static inline void parlio_ll_rx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_rx_eof_cond_t cond)
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{
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dev->rx_cfg0.rx_eof_gen_sel = cond;
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}
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/**
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* @brief Start RX unit to sample the input data
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*
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* @param dev Parallel IO register base address
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* @param en True to start, False to stop
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*/
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static inline void parlio_ll_rx_start(parl_io_dev_t *dev, bool en)
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{
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dev->rx_cfg0.rx_start = en;
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}
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/**
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* @brief Set the receive length
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*
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* @note The receive length can be used to generate DMA EOF signal, or to work as a frame end delimiter
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*
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* @param dev Parallel IO register base address
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* @param bitlen Number of bits to receive in the next transaction, bitlen must be a multiple of 8
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*/
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static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_cfg0, rx_data_bytelen, bitlen / 8);
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}
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/**
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* @brief Set the sub mode of the level controlled receive mode
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*
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* @param dev Parallel IO register base address
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* @param active_level Level of the external enable signal, true for active high, false for active low
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*/
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static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_level)
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{
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dev->rx_cfg0.rx_smp_mode_sel = 0;
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dev->rx_cfg0.rx_level_submode_sel = !active_level; // 0: active low, 1: active high
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}
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/**
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* @brief Set the sub mode of the pulse controlled receive mode
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*
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* @param dev Parallel IO register base address
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* @param start_inc Whether the start pulse is counted
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* @param end_inc Whether the end pulse is counted
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* @param end_by_len Whether to use the frame length to determine the end of the frame
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* @param pulse_inv Whether the pulse is inverted
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*/
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static inline void parlio_ll_rx_set_pulse_recv_mode(parl_io_dev_t *dev, bool start_inc, bool end_inc, bool end_by_len, bool pulse_inv)
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{
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uint32_t submode = 0;
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uint32_t step = 1;
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if (end_by_len) {
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submode += 4;
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} else {
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step = 2;
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if (!end_inc) {
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submode += 1;
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}
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}
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if (!start_inc) {
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submode += step;
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}
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if (pulse_inv) {
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submode += 6;
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}
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dev->rx_cfg0.rx_smp_mode_sel = 1;
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dev->rx_cfg0.rx_pulse_submode_sel = submode;
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}
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/**
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* @brief Set the receive mode to software controlled receive mode
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*
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* @param dev Parallel IO register base address
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*/
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static inline void parlio_ll_rx_set_soft_recv_mode(parl_io_dev_t *dev)
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{
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dev->rx_cfg0.rx_smp_mode_sel = 2;
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}
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/**
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* @brief Whether to start the software controlled receive mode
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
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{
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dev->rx_cfg0.rx_sw_en = en;
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}
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/**
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* @brief Set the sample clock edge
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*
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* @param dev Parallel IO register base address
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* @param edge Sample clock edge
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*/
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static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
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{
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dev->rx_cfg0.rx_clk_edge_sel = edge;
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}
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/**
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* @brief Set the order to pack bits into one byte
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*
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* @param dev Parallel IO register base address
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* @param order Packing order
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*/
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static inline void parlio_ll_rx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
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{
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dev->rx_cfg0.rx_bit_pack_order = order;
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}
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/**
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* @brief Set the bus width of the RX unit
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*
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* @param dev Parallel IO register base address
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* @param width Bus width
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*/
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static inline void parlio_ll_rx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
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{
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uint32_t width_sel = 0;
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switch (width) {
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case 16:
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width_sel = 0;
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break;
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case 8:
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width_sel = 1;
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break;
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case 4:
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width_sel = 2;
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break;
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case 2:
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width_sel = 3;
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break;
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case 1:
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width_sel = 4;
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break;
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default:
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HAL_ASSERT(false);
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}
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dev->rx_cfg0.rx_bus_wid_sel = width_sel;
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}
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/**
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* @brief Reset RX Async FIFO
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*
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* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
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* The reset synchronization must be performed two clock cycles in advance.
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* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
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* and then switch to the actual clock after the reset is completed.
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*
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* @param dev Parallel IO register base address
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev)
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{
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dev->rx_cfg0.rx_fifo_srst = 1;
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dev->rx_cfg0.rx_fifo_srst = 0;
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}
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/**
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* @brief Set which data line as the enable signal
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*
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* @param dev Parallel IO register base address
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* @param line_num Data line number (0-15)
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*/
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static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num)
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{
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dev->rx_cfg1.rx_ext_en_sel = line_num;
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}
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/**
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* @brief Enable RX timeout feature
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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static inline void parlio_ll_rx_enable_timeout(parl_io_dev_t *dev, bool en)
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{
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dev->rx_cfg1.rx_timeout_en = en;
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}
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/**
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* @brief Set the threshold of RX timeout
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*
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* @param dev Parallel IO register base address
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* @param thres Threshold of RX timeout
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*/
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static inline void parlio_ll_rx_set_timeout_thres(parl_io_dev_t *dev, uint32_t thres)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_cfg1, rx_timeout_threshold, thres);
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}
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/**
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* @brief Update the RX configuration, to make the new configuration take effect
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*
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* @param dev Parallel IO register base address
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*/
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static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
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{
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dev->rx_cfg1.rx_reg_update = 1;
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while (dev->rx_cfg1.rx_reg_update);
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}
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///////////////////////////////////TX Unit///////////////////////////////////////
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/**
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* @brief Set the clock source for the TX unit
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*
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* @param dev Parallel IO register base address
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* @param src Clock source
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*/
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static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_ll_clock_source_t src)
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{
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(void)dev;
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uint32_t clk_sel = 0;
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switch (src) {
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case PARLIO_LL_CLK_SRC_XTAL:
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clk_sel = 0;
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break;
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case PARLIO_LL_CLK_SRC_PLL_F240M:
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clk_sel = 1;
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break;
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case PARLIO_LL_CLK_SRC_PAD:
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clk_sel = 3;
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break;
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default: // unsupported clock source
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HAL_ASSERT(false);
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break;
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}
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PCR.parl_clk_tx_conf.parl_clk_tx_sel = clk_sel;
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}
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/**
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* @brief Set the clock divider for the TX unit
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*
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* @param dev Parallel IO register base address
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* @param div Clock divider
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*/
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static inline void parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, uint32_t div)
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{
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(void)dev;
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HAL_ASSERT(div > 0 && div <= PARLIO_LL_TX_MAX_CLOCK_DIV);
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PCR.parl_clk_tx_conf.parl_clk_tx_div_num = div - 1;
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}
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/**
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* @brief Reset the TX unit Core clock domain
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*
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* @param dev Parallel IO register base address
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_tx_reset_clock(parl_io_dev_t *dev)
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{
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(void)dev;
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PCR.parl_clk_tx_conf.parl_tx_rst_en = 1;
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PCR.parl_clk_tx_conf.parl_tx_rst_en = 0;
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}
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/**
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* @brief Enable the TX unit Core clock domain
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
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{
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(void)dev;
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PCR.parl_clk_tx_conf.parl_clk_tx_en = en;
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}
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/**
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* @brief Set the data length to be transmitted
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*
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* @param dev Parallel IO register base address
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* @param bitlen Data length in bits, must be a multiple of 8
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cfg0, tx_bytelen, bitlen / 8);
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}
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/**
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* @brief Wether to enable the TX clock gating
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*
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* @note The TXD[7] will be taken as the gating enable signal
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en)
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{
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dev->tx_cfg0.tx_gating_en = en;
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}
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/**
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* @brief Start TX unit to transmit data
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*
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* @param dev Parallel IO register base address
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* @param en True to start, False to stop
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
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{
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dev->tx_cfg0.tx_start = en;
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}
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/**
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* @brief Whether to treat the MSB of TXD as the valid signal
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*
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* @note If enabled, TXD[15] will work as valid signal, which stay high during data transmission.
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
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{
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dev->tx_cfg0.tx_hw_valid_en = en;
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}
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/**
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* @brief Set the sample clock edge
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*
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* @param dev Parallel IO register base address
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* @param edge Sample clock edge
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*/
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static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
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{
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dev->tx_cfg0.tx_smp_edge_sel = edge;
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}
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/**
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* @brief Set the order to unpack bits from a byte
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*
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* @param dev Parallel IO register base address
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* @param order Packing order
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*/
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static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
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{
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dev->tx_cfg0.tx_bit_unpack_order = order;
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}
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/**
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* @brief Set the bus width of the TX unit
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*
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* @param dev Parallel IO register base address
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* @param width Bus width
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*/
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static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
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{
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uint32_t width_sel = 0;
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switch (width) {
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case 16:
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width_sel = 0;
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break;
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case 8:
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width_sel = 1;
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break;
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case 4:
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width_sel = 2;
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break;
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case 2:
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width_sel = 3;
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break;
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case 1:
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width_sel = 4;
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break;
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default:
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HAL_ASSERT(false);
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}
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dev->tx_cfg0.tx_bus_wid_sel = width_sel;
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}
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/**
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* @brief Reset TX Async FIFO
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*
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* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
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* The reset synchronization must be performed two clock cycles in advance.
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* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
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* and then switch to the actual clock after the reset is completed.
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*
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* @param dev Parallel IO register base address
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev)
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{
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dev->tx_cfg0.tx_fifo_srst = 1;
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dev->tx_cfg0.tx_fifo_srst = 0;
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}
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/**
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* @brief Set the value to output on the TXD when the TX unit is in IDLE state
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|
*
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* @param dev Parallel IO register base address
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|
* @param value Value to output
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|
*/
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|
__attribute__((always_inline))
|
|
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
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|
{
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|
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cfg1, tx_idle_value, value);
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|
}
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|
|
|
/**
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|
* @brief Check whether the TX unit is ready
|
|
*
|
|
* @param dev Parallel IO register base address
|
|
* @return true: ready, false: busy
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline bool parlio_ll_tx_is_ready(parl_io_dev_t *dev)
|
|
{
|
|
return dev->st.tx_ready;
|
|
}
|
|
|
|
////////////////////////////////////Interrupt////////////////////////////////////////////////
|
|
|
|
/**
|
|
* @brief Enable Parallel IO interrupt for specific event mask
|
|
*
|
|
* @param dev Parallel IO register base address
|
|
* @param mask Event mask
|
|
* @param enable True to enable, False to disable
|
|
*/
|
|
static inline void parlio_ll_enable_interrupt(parl_io_dev_t *dev, uint32_t mask, bool enable)
|
|
{
|
|
if (enable) {
|
|
dev->int_ena.val |= mask;
|
|
} else {
|
|
dev->int_ena.val &= ~mask;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Get interrupt status for TX unit
|
|
*
|
|
* @param dev Parallel IO register base address
|
|
* @return Interrupt status
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline uint32_t parlio_ll_tx_get_interrupt_status(parl_io_dev_t *dev)
|
|
{
|
|
return dev->int_st.val & PARLIO_LL_EVENT_TX_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Get interrupt status for RX unit
|
|
*
|
|
* @param dev Parallel IO register base address
|
|
* @return Interrupt status
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline uint32_t parlio_ll_rx_get_interrupt_status(parl_io_dev_t *dev)
|
|
{
|
|
return dev->int_st.val & PARLIO_LL_EVENT_RX_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear Parallel IO interrupt status by mask
|
|
*
|
|
* @param dev Parallel IO register base address
|
|
* @param mask Interrupt status mask
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void parlio_ll_clear_interrupt_status(parl_io_dev_t *dev, uint32_t mask)
|
|
{
|
|
dev->int_clr.val = mask;
|
|
}
|
|
|
|
/**
|
|
* @brief Get interrupt status register address
|
|
*
|
|
* @param dev Parallel IO register base address
|
|
* @return Register address
|
|
*/
|
|
static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *dev)
|
|
{
|
|
return &dev->int_st;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|