mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
79 lines
1.8 KiB
C
79 lines
1.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "esp_private/periph_ctrl.h"
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#ifndef CONFIG_IDF_TARGET_ESP32
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#include "soc/system_reg.h"
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#endif // not CONFIG_IDF_TARGET_ESP32
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#include "soc/rtc.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/rtc.h"
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#include "esp_private/esp_pmu.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32P4
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#include "esp32p4/rom/rtc.h"
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#endif
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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static const char *TAG = "fpga_clk";
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static void s_warn(void)
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{
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ESP_EARLY_LOGE(TAG, "Project configuration is for internal FPGA use, clock functions will not work");
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}
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void bootloader_clock_configure(void)
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{
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s_warn();
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esp_rom_uart_tx_wait_idle(0);
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uint32_t xtal_freq_mhz = 40;
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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uint32_t apb_freq_hz = 20000000;
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#else
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uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000;
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#endif // CONFIG_IDF_TARGET_ESP32S2
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esp_rom_set_cpu_ticks_per_us(apb_freq_hz / 1000000);
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#ifdef RTC_APB_FREQ_REG
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REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
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#endif
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REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
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}
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void esp_clk_init(void)
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{
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s_warn();
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#if SOC_PMU_SUPPORTED
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pmu_init();
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#endif
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}
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void esp_perip_clk_init(void)
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{
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}
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/**
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* @brief No-op function, used to force linking this file
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*
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*/
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void esp_common_include_fpga_overrides_clk(void)
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{
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}
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