Marius Vikhammer c36dd7834f core: fix cases where riscv SP were not 16 byte aligned ... RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.		2021-02-19 11:26:21 +08:00
..
include	Security: ESP32C3 memory protection feature (IRAM0/DRAM0)	2021-01-27 08:44:03 +01:00
CMakeLists.txt	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
expression_with_stack_riscv_asm.S	core: fix cases where riscv SP were not 16 byte aligned	2021-02-19 11:26:21 +08:00
expression_with_stack_riscv.c	core: fix cases where riscv SP were not 16 byte aligned	2021-02-19 11:26:21 +08:00
instruction_decode.c	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
interrupt.c	interrupt: removed descriptor table from esp32c3 interrupt hal.	2021-01-05 15:39:46 +08:00
linker.lf	riscv: Place stdatomic file in iram	2020-12-24 14:18:01 +11:00
stdatomic.c	riscv: Add new arch-level component	2020-11-12 09:33:18 +11:00
vectors.S	Security: ESP32C3 memory protection feature (IRAM0/DRAM0)	2021-01-27 08:44:03 +01:00